[PATCH] D52816: [AArch64] Create proper memoperand for multi-vector stores

[Nirav Dave via Phabricator via llvm-commits]

niravd accepted this revision.
niravd added a comment.
This revision is now accepted and ready to land.

LGTM modulo minor typo .



================
Comment at: test/CodeGen/AArch64/multi-vector-store-size.ll:73
+; The sizes below are conservative.  AArch64TargetLowering
+; conservatively assumes the entiew vector is stored.
+  tail call void @llvm.aarch64.neon.st2lane.v4f32.p0f32(<4 x float> %ar, <4 x float> %br, i64 1, float* %res)
----------------
entire*


Repository:
  rL LLVM

https://reviews.llvm.org/D52816