[PATCH] D53230: [RISCV] Introduce codegen patterns for RV64M-only instructions

[Shiva Chen via Phabricator via llvm-commits]

shiva0217 added a comment.

Probably need to add

  def : Pat<(sext_inreg (sdiv GPR:$rs1, GPR:$rs2), i32),
            (DIVW GPR:$rs1, GPR:$rs2)>;
  def : Pat<(sext_inreg (udiv GPR:$rs1, GPR:$rs2), i32),
            (DIVUW GPR:$rs1, GPR:$rs2)>;

Because DAG combine may create these patterns.

A simple example to observe the pattern:

  int bar (int a, int b)
  {
    return a / b;
  }


https://reviews.llvm.org/D53230