[PATCH] D52846: [AMDGPU] Add FixupVectorISel pass, currently Supports SREGs in GLOBAL LD/ST

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

You probably need to extend the pass to support subregs, not necessarily in the same patch.
But you definitely need a mir test with subregs used with either operands.



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Comment at: lib/Target/AMDGPU/SIFixupVectorISel.cpp:9
+/// \file
+/// SIFixupVectorISel pass cleans up post ISEL Vector issues.
+/// Currently this will convert GLOBAL_{LOAD|STORE}_*
----------------
The name of the pass is too opaque and gives no hint what pass actually doing. I think it needs to have something about "flat" in the name.


================
Comment at: lib/Target/AMDGPU/SIFixupVectorISel.cpp:117
+        continue;
+      IndexReg = MI->getOperand(1).getReg();
+      // Chase the BaseReg.
----------------
Can be subreg.


================
Comment at: lib/Target/AMDGPU/SIFixupVectorISel.cpp:122
+        continue;
+      BaseReg = MI->getOperand(1).getReg();
+      // Make sure Base is SReg and Index is VReg.
----------------
Can be subreg.


https://reviews.llvm.org/D52846