[llvm] r344884 - [X86] Add patterns for vector and/or/xor/andn with other types than vXi64.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Oct 21 23:30:22 PDT 2018
Author: ctopper
Date: Sun Oct 21 23:30:22 2018
New Revision: 344884
URL: http://llvm.org/viewvc/llvm-project?rev=344884&view=rev
Log:
[X86] Add patterns for vector and/or/xor/andn with other types than vXi64.
This makes fast isel treat all legal vector types the same way. Previously only vXi64 was in the fast-isel tables.
This unfortunately prevents matching of andn by fast-isel for these types since the requires SelectionDAG. But we already had this issue for vXi64. So at least we're consistent now.
Interestinly it looks like fast-isel can't handle instructions with constant vector arguments so the the not part of the andn patterns is selected with SelectionDAG. This explains why VPTERNLOG shows up in some of the tests.
This is a subset of D53268. As I make progress on that, I will try to reduce the number of lines in the tablegen files.
Modified:
llvm/trunk/lib/Target/X86/X86InstrAVX512.td
llvm/trunk/lib/Target/X86/X86InstrSSE.td
llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll
llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll
llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrAVX512.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrAVX512.td?rev=344884&r1=344883&r2=344884&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrAVX512.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrAVX512.td Sun Oct 21 23:30:22 2018
@@ -5184,6 +5184,94 @@ defm VPXOR : avx512_logic_rm_vl_dq<0xEF,
defm VPANDN : avx512_logic_rm_vl_dq<0xDF, 0xDF, "vpandn", X86andnp,
SchedWriteVecLogic>;
+let Predicates = [HasVLX] in {
+ def : Pat<(v16i8 (and VR128X:$src1, VR128X:$src2)),
+ (VPANDQZ128rr VR128X:$src1, VR128X:$src2)>;
+ def : Pat<(v8i16 (and VR128X:$src1, VR128X:$src2)),
+ (VPANDQZ128rr VR128X:$src1, VR128X:$src2)>;
+ def : Pat<(v4i32 (and VR128X:$src1, VR128X:$src2)),
+ (VPANDQZ128rr VR128X:$src1, VR128X:$src2)>;
+
+ def : Pat<(v16i8 (or VR128X:$src1, VR128X:$src2)),
+ (VPORQZ128rr VR128X:$src1, VR128X:$src2)>;
+ def : Pat<(v8i16 (or VR128X:$src1, VR128X:$src2)),
+ (VPORQZ128rr VR128X:$src1, VR128X:$src2)>;
+ def : Pat<(v4i32 (or VR128X:$src1, VR128X:$src2)),
+ (VPORQZ128rr VR128X:$src1, VR128X:$src2)>;
+
+ def : Pat<(v16i8 (xor VR128X:$src1, VR128X:$src2)),
+ (VPXORQZ128rr VR128X:$src1, VR128X:$src2)>;
+ def : Pat<(v8i16 (xor VR128X:$src1, VR128X:$src2)),
+ (VPXORQZ128rr VR128X:$src1, VR128X:$src2)>;
+ def : Pat<(v4i32 (xor VR128X:$src1, VR128X:$src2)),
+ (VPXORQZ128rr VR128X:$src1, VR128X:$src2)>;
+
+ def : Pat<(v16i8 (X86andnp VR128X:$src1, VR128X:$src2)),
+ (VPANDNQZ128rr VR128X:$src1, VR128X:$src2)>;
+ def : Pat<(v8i16 (X86andnp VR128X:$src1, VR128X:$src2)),
+ (VPANDNQZ128rr VR128X:$src1, VR128X:$src2)>;
+ def : Pat<(v4i32 (X86andnp VR128X:$src1, VR128X:$src2)),
+ (VPANDNQZ128rr VR128X:$src1, VR128X:$src2)>;
+
+ def : Pat<(v32i8 (and VR256X:$src1, VR256X:$src2)),
+ (VPANDQZ256rr VR256X:$src1, VR256X:$src2)>;
+ def : Pat<(v16i16 (and VR256X:$src1, VR256X:$src2)),
+ (VPANDQZ256rr VR256X:$src1, VR256X:$src2)>;
+ def : Pat<(v8i32 (and VR256X:$src1, VR256X:$src2)),
+ (VPANDQZ256rr VR256X:$src1, VR256X:$src2)>;
+
+ def : Pat<(v32i8 (or VR256X:$src1, VR256X:$src2)),
+ (VPORQZ256rr VR256X:$src1, VR256X:$src2)>;
+ def : Pat<(v16i16 (or VR256X:$src1, VR256X:$src2)),
+ (VPORQZ256rr VR256X:$src1, VR256X:$src2)>;
+ def : Pat<(v8i32 (or VR256X:$src1, VR256X:$src2)),
+ (VPORQZ256rr VR256X:$src1, VR256X:$src2)>;
+
+ def : Pat<(v32i8 (xor VR256X:$src1, VR256X:$src2)),
+ (VPXORQZ256rr VR256X:$src1, VR256X:$src2)>;
+ def : Pat<(v16i16 (xor VR256X:$src1, VR256X:$src2)),
+ (VPXORQZ256rr VR256X:$src1, VR256X:$src2)>;
+ def : Pat<(v8i32 (xor VR256X:$src1, VR256X:$src2)),
+ (VPXORQZ256rr VR256X:$src1, VR256X:$src2)>;
+
+ def : Pat<(v32i8 (X86andnp VR256X:$src1, VR256X:$src2)),
+ (VPANDNQZ256rr VR256X:$src1, VR256X:$src2)>;
+ def : Pat<(v16i16 (X86andnp VR256X:$src1, VR256X:$src2)),
+ (VPANDNQZ256rr VR256X:$src1, VR256X:$src2)>;
+ def : Pat<(v8i32 (X86andnp VR256X:$src1, VR256X:$src2)),
+ (VPANDNQZ256rr VR256X:$src1, VR256X:$src2)>;
+}
+
+let Predicates = [HasAVX512] in {
+ def : Pat<(v64i8 (and VR512:$src1, VR512:$src2)),
+ (VPANDQZrr VR512:$src1, VR512:$src2)>;
+ def : Pat<(v32i16 (and VR512:$src1, VR512:$src2)),
+ (VPANDQZrr VR512:$src1, VR512:$src2)>;
+ def : Pat<(v16i32 (and VR512:$src1, VR512:$src2)),
+ (VPANDQZrr VR512:$src1, VR512:$src2)>;
+
+ def : Pat<(v64i8 (or VR512:$src1, VR512:$src2)),
+ (VPORQZrr VR512:$src1, VR512:$src2)>;
+ def : Pat<(v32i16 (or VR512:$src1, VR512:$src2)),
+ (VPORQZrr VR512:$src1, VR512:$src2)>;
+ def : Pat<(v16i32 (or VR512:$src1, VR512:$src2)),
+ (VPORQZrr VR512:$src1, VR512:$src2)>;
+
+ def : Pat<(v64i8 (xor VR512:$src1, VR512:$src2)),
+ (VPXORQZrr VR512:$src1, VR512:$src2)>;
+ def : Pat<(v32i16 (xor VR512:$src1, VR512:$src2)),
+ (VPXORQZrr VR512:$src1, VR512:$src2)>;
+ def : Pat<(v16i32 (xor VR512:$src1, VR512:$src2)),
+ (VPXORQZrr VR512:$src1, VR512:$src2)>;
+
+ def : Pat<(v64i8 (X86andnp VR512:$src1, VR512:$src2)),
+ (VPANDNQZrr VR512:$src1, VR512:$src2)>;
+ def : Pat<(v32i16 (X86andnp VR512:$src1, VR512:$src2)),
+ (VPANDNQZrr VR512:$src1, VR512:$src2)>;
+ def : Pat<(v16i32 (X86andnp VR512:$src1, VR512:$src2)),
+ (VPANDNQZrr VR512:$src1, VR512:$src2)>;
+}
+
//===----------------------------------------------------------------------===//
// AVX-512 FP arithmetic
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=344884&r1=344883&r2=344884&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Sun Oct 21 23:30:22 2018
@@ -2389,15 +2389,72 @@ defm XOR : sse12_fp_packed_logical<0x57
let isCommutable = 0 in
defm ANDN : sse12_fp_packed_logical<0x55, "andn", X86andnp, SchedWriteFLogic>;
+let Predicates = [HasAVX2, NoVLX] in {
+ def : Pat<(v32i8 (and VR256:$src1, VR256:$src2)),
+ (VPANDYrr VR256:$src1, VR256:$src2)>;
+ def : Pat<(v16i16 (and VR256:$src1, VR256:$src2)),
+ (VPANDYrr VR256:$src1, VR256:$src2)>;
+ def : Pat<(v8i32 (and VR256:$src1, VR256:$src2)),
+ (VPANDYrr VR256:$src1, VR256:$src2)>;
+
+ def : Pat<(v32i8 (or VR256:$src1, VR256:$src2)),
+ (VPORYrr VR256:$src1, VR256:$src2)>;
+ def : Pat<(v16i16 (or VR256:$src1, VR256:$src2)),
+ (VPORYrr VR256:$src1, VR256:$src2)>;
+ def : Pat<(v8i32 (or VR256:$src1, VR256:$src2)),
+ (VPORYrr VR256:$src1, VR256:$src2)>;
+
+ def : Pat<(v32i8 (xor VR256:$src1, VR256:$src2)),
+ (VPXORYrr VR256:$src1, VR256:$src2)>;
+ def : Pat<(v16i16 (xor VR256:$src1, VR256:$src2)),
+ (VPXORYrr VR256:$src1, VR256:$src2)>;
+ def : Pat<(v8i32 (xor VR256:$src1, VR256:$src2)),
+ (VPXORYrr VR256:$src1, VR256:$src2)>;
+
+ def : Pat<(v32i8 (X86andnp VR256:$src1, VR256:$src2)),
+ (VPANDNYrr VR256:$src1, VR256:$src2)>;
+ def : Pat<(v16i16 (X86andnp VR256:$src1, VR256:$src2)),
+ (VPANDNYrr VR256:$src1, VR256:$src2)>;
+ def : Pat<(v8i32 (X86andnp VR256:$src1, VR256:$src2)),
+ (VPANDNYrr VR256:$src1, VR256:$src2)>;
+}
+
// If only AVX1 is supported, we need to handle integer operations with
// floating point instructions since the integer versions aren't available.
let Predicates = [HasAVX1Only] in {
+ def : Pat<(v32i8 (and VR256:$src1, VR256:$src2)),
+ (VANDPSYrr VR256:$src1, VR256:$src2)>;
+ def : Pat<(v16i16 (and VR256:$src1, VR256:$src2)),
+ (VANDPSYrr VR256:$src1, VR256:$src2)>;
+ def : Pat<(v8i32 (and VR256:$src1, VR256:$src2)),
+ (VANDPSYrr VR256:$src1, VR256:$src2)>;
def : Pat<(v4i64 (and VR256:$src1, VR256:$src2)),
(VANDPSYrr VR256:$src1, VR256:$src2)>;
+
+ def : Pat<(v32i8 (or VR256:$src1, VR256:$src2)),
+ (VORPSYrr VR256:$src1, VR256:$src2)>;
+ def : Pat<(v16i16 (or VR256:$src1, VR256:$src2)),
+ (VORPSYrr VR256:$src1, VR256:$src2)>;
+ def : Pat<(v8i32 (or VR256:$src1, VR256:$src2)),
+ (VORPSYrr VR256:$src1, VR256:$src2)>;
def : Pat<(v4i64 (or VR256:$src1, VR256:$src2)),
(VORPSYrr VR256:$src1, VR256:$src2)>;
+
+ def : Pat<(v32i8 (xor VR256:$src1, VR256:$src2)),
+ (VXORPSYrr VR256:$src1, VR256:$src2)>;
+ def : Pat<(v16i16 (xor VR256:$src1, VR256:$src2)),
+ (VXORPSYrr VR256:$src1, VR256:$src2)>;
+ def : Pat<(v8i32 (xor VR256:$src1, VR256:$src2)),
+ (VXORPSYrr VR256:$src1, VR256:$src2)>;
def : Pat<(v4i64 (xor VR256:$src1, VR256:$src2)),
(VXORPSYrr VR256:$src1, VR256:$src2)>;
+
+ def : Pat<(v32i8 (X86andnp VR256:$src1, VR256:$src2)),
+ (VANDNPSYrr VR256:$src1, VR256:$src2)>;
+ def : Pat<(v16i16 (X86andnp VR256:$src1, VR256:$src2)),
+ (VANDNPSYrr VR256:$src1, VR256:$src2)>;
+ def : Pat<(v8i32 (X86andnp VR256:$src1, VR256:$src2)),
+ (VANDNPSYrr VR256:$src1, VR256:$src2)>;
def : Pat<(v4i64 (X86andnp VR256:$src1, VR256:$src2)),
(VANDNPSYrr VR256:$src1, VR256:$src2)>;
@@ -2504,6 +2561,66 @@ let Predicates = [UseSSE2] in {
FR64)>;
}
+let Predicates = [HasAVX, NoVLX] in {
+ def : Pat<(v16i8 (and VR128:$src1, VR128:$src2)),
+ (VPANDrr VR128:$src1, VR128:$src2)>;
+ def : Pat<(v8i16 (and VR128:$src1, VR128:$src2)),
+ (VPANDrr VR128:$src1, VR128:$src2)>;
+ def : Pat<(v4i32 (and VR128:$src1, VR128:$src2)),
+ (VPANDrr VR128:$src1, VR128:$src2)>;
+
+ def : Pat<(v16i8 (or VR128:$src1, VR128:$src2)),
+ (VPORrr VR128:$src1, VR128:$src2)>;
+ def : Pat<(v8i16 (or VR128:$src1, VR128:$src2)),
+ (VPORrr VR128:$src1, VR128:$src2)>;
+ def : Pat<(v4i32 (or VR128:$src1, VR128:$src2)),
+ (VPORrr VR128:$src1, VR128:$src2)>;
+
+ def : Pat<(v16i8 (xor VR128:$src1, VR128:$src2)),
+ (VPXORrr VR128:$src1, VR128:$src2)>;
+ def : Pat<(v8i16 (xor VR128:$src1, VR128:$src2)),
+ (VPXORrr VR128:$src1, VR128:$src2)>;
+ def : Pat<(v4i32 (xor VR128:$src1, VR128:$src2)),
+ (VPXORrr VR128:$src1, VR128:$src2)>;
+
+ def : Pat<(v16i8 (X86andnp VR128:$src1, VR128:$src2)),
+ (VPANDNrr VR128:$src1, VR128:$src2)>;
+ def : Pat<(v8i16 (X86andnp VR128:$src1, VR128:$src2)),
+ (VPANDNrr VR128:$src1, VR128:$src2)>;
+ def : Pat<(v4i32 (X86andnp VR128:$src1, VR128:$src2)),
+ (VPANDNrr VR128:$src1, VR128:$src2)>;
+}
+
+let Predicates = [UseSSE2] in {
+ def : Pat<(v16i8 (and VR128:$src1, VR128:$src2)),
+ (PANDrr VR128:$src1, VR128:$src2)>;
+ def : Pat<(v8i16 (and VR128:$src1, VR128:$src2)),
+ (PANDrr VR128:$src1, VR128:$src2)>;
+ def : Pat<(v4i32 (and VR128:$src1, VR128:$src2)),
+ (PANDrr VR128:$src1, VR128:$src2)>;
+
+ def : Pat<(v16i8 (or VR128:$src1, VR128:$src2)),
+ (PORrr VR128:$src1, VR128:$src2)>;
+ def : Pat<(v8i16 (or VR128:$src1, VR128:$src2)),
+ (PORrr VR128:$src1, VR128:$src2)>;
+ def : Pat<(v4i32 (or VR128:$src1, VR128:$src2)),
+ (PORrr VR128:$src1, VR128:$src2)>;
+
+ def : Pat<(v16i8 (xor VR128:$src1, VR128:$src2)),
+ (PXORrr VR128:$src1, VR128:$src2)>;
+ def : Pat<(v8i16 (xor VR128:$src1, VR128:$src2)),
+ (PXORrr VR128:$src1, VR128:$src2)>;
+ def : Pat<(v4i32 (xor VR128:$src1, VR128:$src2)),
+ (PXORrr VR128:$src1, VR128:$src2)>;
+
+ def : Pat<(v16i8 (X86andnp VR128:$src1, VR128:$src2)),
+ (PANDNrr VR128:$src1, VR128:$src2)>;
+ def : Pat<(v8i16 (X86andnp VR128:$src1, VR128:$src2)),
+ (PANDNrr VR128:$src1, VR128:$src2)>;
+ def : Pat<(v4i32 (X86andnp VR128:$src1, VR128:$src2)),
+ (PANDNrr VR128:$src1, VR128:$src2)>;
+}
+
// Patterns for packed operations when we don't have integer type available.
def : Pat<(v4f32 (X86fand VR128:$src1, VR128:$src2)),
(ANDPSrr VR128:$src1, VR128:$src2)>;
Modified: llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll?rev=344884&r1=344883&r2=344884&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll (original)
+++ llvm/trunk/test/CodeGen/X86/avx-intrinsics-fast-isel.ll Sun Oct 21 23:30:22 2018
@@ -85,7 +85,10 @@ define <4 x double> @test_mm256_andnot_p
define <8 x float> @test_mm256_andnot_ps(<8 x float> %a0, <8 x float> %a1) nounwind {
; CHECK-LABEL: test_mm256_andnot_ps:
; CHECK: # %bb.0:
-; CHECK-NEXT: vandnps %ymm1, %ymm0, %ymm0
+; CHECK-NEXT: vxorps %xmm2, %xmm2, %xmm2
+; CHECK-NEXT: vcmptrueps %ymm2, %ymm2, %ymm2
+; CHECK-NEXT: vxorps %ymm2, %ymm0, %ymm0
+; CHECK-NEXT: vandps %ymm1, %ymm0, %ymm0
; CHECK-NEXT: ret{{[l|q]}}
%1 = bitcast <8 x float> %a0 to <8 x i32>
%2 = bitcast <8 x float> %a1 to <8 x i32>
Modified: llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll?rev=344884&r1=344883&r2=344884&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse-intrinsics-fast-isel.ll Sun Oct 21 23:30:22 2018
@@ -79,12 +79,15 @@ define <4 x float> @test_mm_andnot_ps(<4
;
; AVX1-LABEL: test_mm_andnot_ps:
; AVX1: # %bb.0:
-; AVX1-NEXT: vandnps %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x55,0xc1]
+; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 # encoding: [0xc5,0xe9,0x76,0xd2]
+; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0xef,0xc2]
+; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0xdb,0xc1]
; AVX1-NEXT: ret{{[l|q]}} # encoding: [0xc3]
;
; AVX512-LABEL: test_mm_andnot_ps:
; AVX512: # %bb.0:
-; AVX512-NEXT: vandnps %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x55,0xc1]
+; AVX512-NEXT: vpternlogq $15, %xmm0, %xmm0, %xmm0 # encoding: [0x62,0xf3,0xfd,0x08,0x25,0xc0,0x0f]
+; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0xdb,0xc1]
; AVX512-NEXT: ret{{[l|q]}} # encoding: [0xc3]
%arg0 = bitcast <4 x float> %a0 to <4 x i32>
%arg1 = bitcast <4 x float> %a1 to <4 x i32>
Modified: llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll?rev=344884&r1=344883&r2=344884&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse2-intrinsics-fast-isel.ll Sun Oct 21 23:30:22 2018
@@ -272,17 +272,22 @@ define <2 x i64> @test_mm_and_si128(<2 x
define <2 x double> @test_mm_andnot_pd(<2 x double> %a0, <2 x double> %a1) nounwind {
; SSE-LABEL: test_mm_andnot_pd:
; SSE: # %bb.0:
-; SSE-NEXT: andnps %xmm1, %xmm0 # encoding: [0x0f,0x55,0xc1]
+; SSE-NEXT: pcmpeqd %xmm2, %xmm2 # encoding: [0x66,0x0f,0x76,0xd2]
+; SSE-NEXT: pxor %xmm2, %xmm0 # encoding: [0x66,0x0f,0xef,0xc2]
+; SSE-NEXT: pand %xmm1, %xmm0 # encoding: [0x66,0x0f,0xdb,0xc1]
; SSE-NEXT: ret{{[l|q]}} # encoding: [0xc3]
;
; AVX1-LABEL: test_mm_andnot_pd:
; AVX1: # %bb.0:
-; AVX1-NEXT: vandnps %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf8,0x55,0xc1]
+; AVX1-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2 # encoding: [0xc5,0xe9,0x76,0xd2]
+; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0xef,0xc2]
+; AVX1-NEXT: vpand %xmm1, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0xdb,0xc1]
; AVX1-NEXT: ret{{[l|q]}} # encoding: [0xc3]
;
; AVX512-LABEL: test_mm_andnot_pd:
; AVX512: # %bb.0:
-; AVX512-NEXT: vandnps %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x55,0xc1]
+; AVX512-NEXT: vpternlogq $15, %xmm0, %xmm0, %xmm0 # encoding: [0x62,0xf3,0xfd,0x08,0x25,0xc0,0x0f]
+; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 # EVEX TO VEX Compression encoding: [0xc5,0xf9,0xdb,0xc1]
; AVX512-NEXT: ret{{[l|q]}} # encoding: [0xc3]
%arg0 = bitcast <2 x double> %a0 to <4 x i32>
%arg1 = bitcast <2 x double> %a1 to <4 x i32>
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