[PATCH] D53438: [llvm-exegesis] Reject x86 instructions that use non uniform memory accesses

[Guillaume Chatelet via Phabricator via llvm-commits]

gchatelet created this revision.
gchatelet added a reviewer: courbet.
Herald added subscribers: llvm-commits, tschuett.

Repository:
  rL LLVM

https://reviews.llvm.org/D53438

Files:
  tools/llvm-exegesis/lib/X86/Target.cpp


Index: tools/llvm-exegesis/lib/X86/Target.cpp
===================================================================
--- tools/llvm-exegesis/lib/X86/Target.cpp
+++ tools/llvm-exegesis/lib/X86/Target.cpp
@@ -21,12 +21,44 @@
 
 namespace {
 
+static bool isMemoryOperand(const Operand &Op) {
+  return Op.isMemory() && Op.isExplicit();
+}
+
+static std::vector<llvm::ArrayRef<Operand>>
+getMemoryOperandRanges(llvm::ArrayRef<Operand> Operands) {
+  std::vector<llvm::ArrayRef<Operand>> Result;
+  while (!Operands.empty()) {
+    Operands = Operands.drop_until(isMemoryOperand);
+    auto MemoryOps = Operands.take_while(isMemoryOperand);
+    if (!MemoryOps.empty())
+      Result.push_back(MemoryOps);
+    Operands = Operands.drop_front(MemoryOps.size());
+  }
+  return Result;
+}
+
+static bool isValidMemoryOperandRange(llvm::ArrayRef<Operand> Range) {
+  return Range.size() == 5;
+}
+
 static llvm::Error IsInvalidOpcode(const Instruction &Instr) {
   const auto OpcodeName = Instr.Name;
   if (OpcodeName.startswith("POPF") || OpcodeName.startswith("PUSHF") ||
       OpcodeName.startswith("ADJCALLSTACK"))
     return llvm::make_error<BenchmarkFailure>(
         "unsupported opcode: Push/Pop/AdjCallStack");
+  const bool ValidMemoryOperands = llvm::all_of(
+      getMemoryOperandRanges(Instr.Operands), isValidMemoryOperandRange);
+  if (!ValidMemoryOperands)
+    return llvm::make_error<BenchmarkFailure>(
+        "unsupported opcode: non uniform memory access");
+  // We do not handle instructions with OPERAND_PCREL.
+  for (const Operand &Op : Instr.Operands)
+    if (Op.isExplicit() &&
+        Op.getExplicitOperandInfo().OperandType == llvm::MCOI ::OPERAND_PCREL)
+      return llvm::make_error<BenchmarkFailure>(
+          "unsupported opcode: PC relative operand");
   // We do not handle second-form X87 instructions. We only handle first-form
   // ones (_Fp), see comment in X86InstrFPStack.td.
   for (const Operand &Op : Instr.Operands)
@@ -281,29 +313,19 @@
                           unsigned Offset) const override {
     // FIXME: For instructions that read AND write to memory, we use the same
     // value for input and output.
-    for (size_t I = 0, E = IT.Instr.Operands.size(); I < E; ++I) {
-      const Operand *Op = &IT.Instr.Operands[I];
-      if (Op->isExplicit() && Op->isMemory()) {
-        // Case 1: 5-op memory.
-        assert((I + 5 <= E) && "x86 memory references are always 5 ops");
-        IT.getValueFor(*Op) = llvm::MCOperand::createReg(Reg); // BaseReg
-        Op = &IT.Instr.Operands[++I];
-        assert(Op->isMemory());
-        assert(Op->isExplicit());
-        IT.getValueFor(*Op) = llvm::MCOperand::createImm(1); // ScaleAmt
-        Op = &IT.Instr.Operands[++I];
-        assert(Op->isMemory());
-        assert(Op->isExplicit());
-        IT.getValueFor(*Op) = llvm::MCOperand::createReg(0); // IndexReg
-        Op = &IT.Instr.Operands[++I];
-        assert(Op->isMemory());
-        assert(Op->isExplicit());
-        IT.getValueFor(*Op) = llvm::MCOperand::createImm(Offset); // Disp
-        Op = &IT.Instr.Operands[++I];
-        assert(Op->isMemory());
-        assert(Op->isExplicit());
-        IT.getValueFor(*Op) = llvm::MCOperand::createReg(0); // Segment
-        // Case2: segment:index addressing. We assume that ES is 0.
+    for (auto Ops : getMemoryOperandRanges(IT.Instr.Operands)) {
+      switch (Ops.size()) {
+      case 5:
+        IT.getValueFor(Ops[0]) = llvm::MCOperand::createReg(Reg);    // BaseReg
+        IT.getValueFor(Ops[1]) = llvm::MCOperand::createImm(1);      // ScaleAmt
+        IT.getValueFor(Ops[2]) = llvm::MCOperand::createReg(0);      // IndexReg
+        IT.getValueFor(Ops[3]) = llvm::MCOperand::createImm(Offset); // Disp
+        IT.getValueFor(Ops[4]) = llvm::MCOperand::createReg(0);      // Segment
+        break;
+      default:
+        llvm::errs() << Ops.size() << "-op are not handled right now ("
+                     << IT.Instr.Name << ")\n";
+        llvm_unreachable("Invalid memory configuration");
       }
     }
   }


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