[PATCH] D53160: AMDGPU: Avoid selecting ds_{read,write}2_b32 on SI

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

Yes, something like this. I still expected to see some change in SelectDS64Bit4ByteAligned that has the fixme for this bug? I suppose the check for the sign bit would need to be here in the lowering since it would be more difficult to split during selection



================
Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:6711
+    if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS &&
+        NumElements == 2 && VT.getStoreSize() == 8 &&
+        Store->getAlignment() < 8) {
----------------
NumElements == 2 is redundant and possibly wrong?


Repository:
  rL LLVM

https://reviews.llvm.org/D53160