[llvm] r344629 - [Intrinsic] Signed Saturation Addition Intrinsic
Leonard Chan via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 16 10:35:42 PDT 2018
Author: leonardchan
Date: Tue Oct 16 10:35:41 2018
New Revision: 344629
URL: http://llvm.org/viewvc/llvm-project?rev=344629&view=rev
Log:
[Intrinsic] Signed Saturation Addition Intrinsic
Add an intrinsic that takes 2 integers and perform saturation addition on them.
This is a part of implementing fixed point arithmetic in clang where some of
the more complex operations will be implemented as intrinsics.
Differential Revision: https://reviews.llvm.org/D53053
Added:
llvm/trunk/test/CodeGen/X86/sadd_sat.ll
Modified:
llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h
llvm/trunk/include/llvm/CodeGen/TargetLowering.h
llvm/trunk/include/llvm/IR/Intrinsics.td
llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp
llvm/trunk/lib/IR/Verifier.cpp
Modified: llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h?rev=344629&r1=344628&r2=344629&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h Tue Oct 16 10:35:41 2018
@@ -256,6 +256,14 @@ namespace ISD {
/// Same for multiplication.
SMULO, UMULO,
+ /// RESULT = SADDSAT(LHS, RHS) - Perform signed saturation addition on 2
+ /// integers with the same bit width (W). If the true value of LHS + RHS
+ /// exceeds the largest signed value that can be represented by W bits, the
+ /// resulting value is this maximum value. Otherwise, if this value is less
+ /// than the smallest signed value that can be represented by W bits, the
+ /// resulting value is this minimum value.
+ SADDSAT,
+
/// Simple binary floating point operators.
FADD, FSUB, FMUL, FDIV, FREM,
Modified: llvm/trunk/include/llvm/CodeGen/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetLowering.h?rev=344629&r1=344628&r2=344629&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/CodeGen/TargetLowering.h Tue Oct 16 10:35:41 2018
@@ -3681,6 +3681,11 @@ public:
SDValue getVectorElementPointer(SelectionDAG &DAG, SDValue VecPtr, EVT VecVT,
SDValue Index) const;
+ /// Method for building the DAG expansion of ISD::SADDSAT. This method accepts
+ /// integers or vectors of integers as its arguments.
+ SDValue getExpandedSignedSaturationAddition(SDNode *Node,
+ SelectionDAG &DAG) const;
+
//===--------------------------------------------------------------------===//
// Instruction Emitting Hooks
//
Modified: llvm/trunk/include/llvm/IR/Intrinsics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IR/Intrinsics.td?rev=344629&r1=344628&r2=344629&view=diff
==============================================================================
--- llvm/trunk/include/llvm/IR/Intrinsics.td (original)
+++ llvm/trunk/include/llvm/IR/Intrinsics.td Tue Oct 16 10:35:41 2018
@@ -708,6 +708,12 @@ def int_umul_with_overflow : Intrinsic<[
[LLVMMatchType<0>, LLVMMatchType<0>],
[IntrNoMem, IntrSpeculatable]>;
+//===------------------------- Fixed Point Intrinsics ---------------------===//
+//
+def int_sadd_sat : Intrinsic<[llvm_anyint_ty],
+ [LLVMMatchType<0>, LLVMMatchType<0>],
+ [IntrNoMem, IntrSpeculatable, Commutative]>;
+
//===------------------------- Memory Use Markers -------------------------===//
//
def int_lifetime_start : Intrinsic<[],
Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=344629&r1=344628&r2=344629&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original)
+++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Tue Oct 16 10:35:41 2018
@@ -373,6 +373,8 @@ def umin : SDNode<"ISD::UMIN"
def umax : SDNode<"ISD::UMAX" , SDTIntBinOp,
[SDNPCommutative, SDNPAssociative]>;
+def saddsat : SDNode<"ISD::SADDSAT" , SDTIntBinOp, [SDNPCommutative]>;
+
def sext_inreg : SDNode<"ISD::SIGN_EXTEND_INREG", SDTExtInreg>;
def sext_invec : SDNode<"ISD::SIGN_EXTEND_VECTOR_INREG", SDTExtInvec>;
def zext_invec : SDNode<"ISD::ZERO_EXTEND_VECTOR_INREG", SDTExtInvec>;
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=344629&r1=344628&r2=344629&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Oct 16 10:35:41 2018
@@ -1115,6 +1115,10 @@ void SelectionDAGLegalize::LegalizeOp(SD
Action = TLI.getStrictFPOperationAction(Node->getOpcode(),
Node->getValueType(0));
break;
+ case ISD::SADDSAT: {
+ Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
+ break;
+ }
case ISD::MSCATTER:
Action = TLI.getOperationAction(Node->getOpcode(),
cast<MaskedScatterSDNode>(Node)->getValue().getValueType());
@@ -3451,6 +3455,10 @@ bool SelectionDAGLegalize::ExpandNode(SD
}
break;
}
+ case ISD::SADDSAT: {
+ Results.push_back(TLI.getExpandedSignedSaturationAddition(Node, DAG));
+ break;
+ }
case ISD::SADDO:
case ISD::SSUBO: {
SDValue LHS = Node->getOperand(0);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=344629&r1=344628&r2=344629&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Tue Oct 16 10:35:41 2018
@@ -141,6 +141,8 @@ void DAGTypeLegalizer::PromoteIntegerRes
case ISD::ADDCARRY:
case ISD::SUBCARRY: Res = PromoteIntRes_ADDSUBCARRY(N, ResNo); break;
+ case ISD::SADDSAT: Res = PromoteIntRes_SADDSAT(N); break;
+
case ISD::ATOMIC_LOAD:
Res = PromoteIntRes_Atomic0(cast<AtomicSDNode>(N)); break;
@@ -546,6 +548,35 @@ SDValue DAGTypeLegalizer::PromoteIntRes_
return SDValue(Res.getNode(), 1);
}
+SDValue DAGTypeLegalizer::PromoteIntRes_SADDSAT(SDNode *N) {
+ // For promoting iN -> iM, this can be expanded by
+ // 1. ANY_EXTEND iN to iM
+ // 2. SHL by M-N
+ // 3. SADDSAT
+ // 4. ASHR by M-N
+ SDLoc dl(N);
+ SDValue Op1 = N->getOperand(0);
+ SDValue Op2 = N->getOperand(1);
+ unsigned OldBits = Op1.getValueSizeInBits();
+
+ SDValue Op1Promoted = GetPromotedInteger(Op1);
+ SDValue Op2Promoted = GetPromotedInteger(Op2);
+
+ EVT PromotedType = Op1Promoted.getValueType();
+ unsigned NewBits = Op1Promoted.getValueSizeInBits();
+ unsigned SHLAmount = NewBits - OldBits;
+ EVT SHVT = TLI.getShiftAmountTy(PromotedType, DAG.getDataLayout());
+ SDValue ShiftAmount = DAG.getConstant(SHLAmount, dl, SHVT);
+ Op1Promoted =
+ DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount);
+ Op2Promoted =
+ DAG.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount);
+
+ SDValue Result =
+ DAG.getNode(ISD::SADDSAT, dl, PromotedType, Op1Promoted, Op2Promoted);
+ return DAG.getNode(ISD::SRA, dl, PromotedType, Result, ShiftAmount);
+}
+
SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) {
if (ResNo == 1)
return PromoteIntRes_Overflow(N);
@@ -1466,6 +1497,8 @@ void DAGTypeLegalizer::ExpandIntegerResu
case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
case ISD::UMULO:
case ISD::SMULO: ExpandIntRes_XMULO(N, Lo, Hi); break;
+
+ case ISD::SADDSAT: ExpandIntRes_SADDSAT(N, Lo, Hi); break;
}
// If Lo/Hi is null, the sub-method took care of registering results etc.
@@ -2428,6 +2461,12 @@ void DAGTypeLegalizer::ExpandIntRes_READ
ReplaceValueWith(SDValue(N, 1), R.getValue(2));
}
+void DAGTypeLegalizer::ExpandIntRes_SADDSAT(SDNode *N, SDValue &Lo,
+ SDValue &Hi) {
+ SDValue Result = TLI.getExpandedSignedSaturationAddition(N, DAG);
+ SplitInteger(Result, Lo, Hi);
+}
+
void DAGTypeLegalizer::ExpandIntRes_SADDSUBO(SDNode *Node,
SDValue &Lo, SDValue &Hi) {
SDValue LHS = Node->getOperand(0);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=344629&r1=344628&r2=344629&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Tue Oct 16 10:35:41 2018
@@ -330,6 +330,7 @@ private:
SDValue PromoteIntRes_UNDEF(SDNode *N);
SDValue PromoteIntRes_VAARG(SDNode *N);
SDValue PromoteIntRes_XMULO(SDNode *N, unsigned ResNo);
+ SDValue PromoteIntRes_SADDSAT(SDNode *N);
// Integer Operand Promotion.
bool PromoteIntegerOperand(SDNode *N, unsigned OpNo);
@@ -414,6 +415,7 @@ private:
void ExpandIntRes_SADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_UADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_XMULO (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandIntRes_SADDSAT (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_ATOMIC_LOAD (SDNode *N, SDValue &Lo, SDValue &Hi);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp?rev=344629&r1=344628&r2=344629&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp Tue Oct 16 10:35:41 2018
@@ -386,6 +386,7 @@ SDValue VectorLegalizer::LegalizeOp(SDVa
case ISD::SMUL_LOHI:
case ISD::UMUL_LOHI:
case ISD::FCANONICALIZE:
+ case ISD::SADDSAT:
Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0));
break;
case ISD::FP_ROUND_INREG:
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=344629&r1=344628&r2=344629&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Tue Oct 16 10:35:41 2018
@@ -120,6 +120,8 @@ void DAGTypeLegalizer::ScalarizeVectorRe
case ISD::UMIN:
case ISD::UMAX:
+ case ISD::SADDSAT:
+
case ISD::FPOW:
case ISD::FREM:
case ISD::FSUB:
@@ -800,6 +802,7 @@ void DAGTypeLegalizer::SplitVectorResult
case ISD::SMAX:
case ISD::UMIN:
case ISD::UMAX:
+ case ISD::SADDSAT:
SplitVecRes_BinOp(N, Lo, Hi);
break;
case ISD::FMA:
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=344629&r1=344628&r2=344629&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Tue Oct 16 10:35:41 2018
@@ -5771,6 +5771,12 @@ SelectionDAGBuilder::visitIntrinsicCall(
setValue(&I, DAG.getSelect(sdl, VT, IsZeroShift, IsFSHL ? X : Y, Or));
return nullptr;
}
+ case Intrinsic::sadd_sat: {
+ SDValue Op1 = getValue(I.getArgOperand(0));
+ SDValue Op2 = getValue(I.getArgOperand(1));
+ setValue(&I, DAG.getNode(ISD::SADDSAT, sdl, Op1.getValueType(), Op1, Op2));
+ return nullptr;
+ }
case Intrinsic::stacksave: {
SDValue Op = getRoot();
Res = DAG.getNode(
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp?rev=344629&r1=344628&r2=344629&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp Tue Oct 16 10:35:41 2018
@@ -282,6 +282,8 @@ std::string SDNode::getOperationName(con
case ISD::SRA_PARTS: return "sra_parts";
case ISD::SRL_PARTS: return "srl_parts";
+ case ISD::SADDSAT: return "saddsat";
+
// Conversion operators.
case ISD::SIGN_EXTEND: return "sign_extend";
case ISD::ZERO_EXTEND: return "zero_extend";
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=344629&r1=344628&r2=344629&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Tue Oct 16 10:35:41 2018
@@ -4651,3 +4651,46 @@ SDValue TargetLowering::lowerCmpEqZeroTo
}
return SDValue();
}
+
+SDValue
+TargetLowering::getExpandedSignedSaturationAddition(SDNode *Node,
+ SelectionDAG &DAG) const {
+ assert(Node->getOpcode() == ISD::SADDSAT &&
+ "Expected method to receive SADDSAT node.");
+ assert(Node->getNumOperands() == 2 &&
+ "Expected SADDSAT node to have 2 operands.");
+
+ SDLoc dl(Node);
+ SDValue LHS = Node->getOperand(0);
+ SDValue RHS = Node->getOperand(1);
+ assert(LHS.getValueType().isScalarInteger() &&
+ "Expected operands to be integers. Vector of int arguments should "
+ "already be unrolled.");
+ assert(RHS.getValueType().isScalarInteger() &&
+ "Expected operands to be integers. Vector of int arguments should "
+ "already be unrolled.");
+ assert(LHS.getValueType() == RHS.getValueType() &&
+ "Expected both operands of SADDSAT to be the same type");
+
+ unsigned BitWidth = LHS.getValueSizeInBits();
+ EVT ResultType = LHS.getValueType();
+ EVT BoolVT =
+ getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), ResultType);
+ SDValue Result =
+ DAG.getNode(ISD::SADDO, dl, DAG.getVTList(ResultType, BoolVT), LHS, RHS);
+ SDValue Sum = Result.getValue(0);
+ SDValue Overflow = Result.getValue(1);
+
+ // SatMax -> Overflow && Sum < 0
+ // SatMin -> Overflow && Sum > 0
+ SDValue Zero = DAG.getConstant(0, dl, LHS.getValueType());
+
+ SDValue SumNeg = DAG.getSetCC(dl, BoolVT, Sum, Zero, ISD::SETLT);
+ APInt MinVal = APInt::getSignedMinValue(BitWidth);
+ APInt MaxVal = APInt::getSignedMaxValue(BitWidth);
+ SDValue SatMin = DAG.getConstant(MinVal, dl, ResultType);
+ SDValue SatMax = DAG.getConstant(MaxVal, dl, ResultType);
+
+ Result = DAG.getSelect(dl, ResultType, SumNeg, SatMax, SatMin);
+ return DAG.getSelect(dl, ResultType, Overflow, Result, Sum);
+}
Modified: llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp?rev=344629&r1=344628&r2=344629&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp Tue Oct 16 10:35:41 2018
@@ -608,6 +608,7 @@ void TargetLoweringBase::initActions() {
setOperationAction(ISD::UMIN, VT, Expand);
setOperationAction(ISD::UMAX, VT, Expand);
setOperationAction(ISD::ABS, VT, Expand);
+ setOperationAction(ISD::SADDSAT, VT, Expand);
// Overflow operations default to expand
setOperationAction(ISD::SADDO, VT, Expand);
Modified: llvm/trunk/lib/IR/Verifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/IR/Verifier.cpp?rev=344629&r1=344628&r2=344629&view=diff
==============================================================================
--- llvm/trunk/lib/IR/Verifier.cpp (original)
+++ llvm/trunk/lib/IR/Verifier.cpp Tue Oct 16 10:35:41 2018
@@ -4474,6 +4474,15 @@ void Verifier::visitIntrinsicCallSite(In
break;
}
+ case Intrinsic::sadd_sat: {
+ Value *Op1 = CS.getArgOperand(0);
+ Value *Op2 = CS.getArgOperand(1);
+ Assert(Op1->getType()->isIntOrIntVectorTy(),
+ "first operand of sadd_sat must be an int type or vector of ints");
+ Assert(Op2->getType()->isIntOrIntVectorTy(),
+ "second operand of sadd_sat must be an int type or vector of ints");
+ break;
+ }
};
}
Added: llvm/trunk/test/CodeGen/X86/sadd_sat.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sadd_sat.ll?rev=344629&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sadd_sat.ll (added)
+++ llvm/trunk/test/CodeGen/X86/sadd_sat.ll Tue Oct 16 10:35:41 2018
@@ -0,0 +1,267 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux | FileCheck %s
+; RUN: llc < %s -mcpu=generic -mtriple=i686 -mattr=cmov | FileCheck %s --check-prefix=CHECK32
+
+declare i4 @llvm.sadd.sat.i4 (i4, i4)
+declare i32 @llvm.sadd.sat.i32 (i32, i32)
+declare i64 @llvm.sadd.sat.i64 (i64, i64)
+declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32>, <4 x i32>)
+
+define i32 @func(i32 %x, i32 %y) {
+; CHECK-LABEL: func:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: movl %edi, %ecx
+; CHECK-NEXT: addl %esi, %ecx
+; CHECK-NEXT: setns %al
+; CHECK-NEXT: addl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK-NEXT: addl %esi, %edi
+; CHECK-NEXT: cmovnol %edi, %eax
+; CHECK-NEXT: retq
+;
+; CHECK32-LABEL: func:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: pushl %esi
+; CHECK32-NEXT: .cfi_def_cfa_offset 8
+; CHECK32-NEXT: .cfi_offset %esi, -8
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
+; CHECK32-NEXT: xorl %ecx, %ecx
+; CHECK32-NEXT: movl %eax, %esi
+; CHECK32-NEXT: addl %edx, %esi
+; CHECK32-NEXT: setns %cl
+; CHECK32-NEXT: addl $2147483647, %ecx # imm = 0x7FFFFFFF
+; CHECK32-NEXT: addl %edx, %eax
+; CHECK32-NEXT: cmovol %ecx, %eax
+; CHECK32-NEXT: popl %esi
+; CHECK32-NEXT: .cfi_def_cfa_offset 4
+; CHECK32-NEXT: retl
+ %tmp = call i32 @llvm.sadd.sat.i32(i32 %x, i32 %y);
+ ret i32 %tmp;
+}
+
+define i64 @func2(i64 %x, i64 %y) {
+; CHECK-LABEL: func2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: xorl %ecx, %ecx
+; CHECK-NEXT: movq %rdi, %rax
+; CHECK-NEXT: addq %rsi, %rax
+; CHECK-NEXT: setns %cl
+; CHECK-NEXT: movabsq $9223372036854775807, %rax # imm = 0x7FFFFFFFFFFFFFFF
+; CHECK-NEXT: addq %rcx, %rax
+; CHECK-NEXT: addq %rsi, %rdi
+; CHECK-NEXT: cmovnoq %rdi, %rax
+; CHECK-NEXT: retq
+;
+; CHECK32-LABEL: func2:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: pushl %ebp
+; CHECK32-NEXT: .cfi_def_cfa_offset 8
+; CHECK32-NEXT: pushl %ebx
+; CHECK32-NEXT: .cfi_def_cfa_offset 12
+; CHECK32-NEXT: pushl %edi
+; CHECK32-NEXT: .cfi_def_cfa_offset 16
+; CHECK32-NEXT: pushl %esi
+; CHECK32-NEXT: .cfi_def_cfa_offset 20
+; CHECK32-NEXT: .cfi_offset %esi, -20
+; CHECK32-NEXT: .cfi_offset %edi, -16
+; CHECK32-NEXT: .cfi_offset %ebx, -12
+; CHECK32-NEXT: .cfi_offset %ebp, -8
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edi
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ebx
+; CHECK32-NEXT: addl {{[0-9]+}}(%esp), %edi
+; CHECK32-NEXT: movl %ebx, %ebp
+; CHECK32-NEXT: adcl %esi, %ebp
+; CHECK32-NEXT: movl %ebp, %eax
+; CHECK32-NEXT: sarl $31, %eax
+; CHECK32-NEXT: xorl %ecx, %ecx
+; CHECK32-NEXT: testl %ebp, %ebp
+; CHECK32-NEXT: setns %cl
+; CHECK32-NEXT: movl %ecx, %edx
+; CHECK32-NEXT: addl $2147483647, %edx # imm = 0x7FFFFFFF
+; CHECK32-NEXT: testl %ebx, %ebx
+; CHECK32-NEXT: setns %bl
+; CHECK32-NEXT: cmpb %cl, %bl
+; CHECK32-NEXT: setne %cl
+; CHECK32-NEXT: testl %esi, %esi
+; CHECK32-NEXT: setns %ch
+; CHECK32-NEXT: cmpb %ch, %bl
+; CHECK32-NEXT: sete %ch
+; CHECK32-NEXT: testb %cl, %ch
+; CHECK32-NEXT: cmovel %ebp, %edx
+; CHECK32-NEXT: cmovel %edi, %eax
+; CHECK32-NEXT: popl %esi
+; CHECK32-NEXT: .cfi_def_cfa_offset 16
+; CHECK32-NEXT: popl %edi
+; CHECK32-NEXT: .cfi_def_cfa_offset 12
+; CHECK32-NEXT: popl %ebx
+; CHECK32-NEXT: .cfi_def_cfa_offset 8
+; CHECK32-NEXT: popl %ebp
+; CHECK32-NEXT: .cfi_def_cfa_offset 4
+; CHECK32-NEXT: retl
+ %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y);
+ ret i64 %tmp;
+}
+
+define i4 @func3(i4 %x, i4 %y) {
+; CHECK-LABEL: func3:
+; CHECK: # %bb.0:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: shlb $4, %sil
+; CHECK-NEXT: shlb $4, %al
+; CHECK-NEXT: movl %eax, %ecx
+; CHECK-NEXT: addb %sil, %cl
+; CHECK-NEXT: setns %cl
+; CHECK-NEXT: addb %sil, %al
+; CHECK-NEXT: jno .LBB2_2
+; CHECK-NEXT: # %bb.1:
+; CHECK-NEXT: addb $127, %cl
+; CHECK-NEXT: movl %ecx, %eax
+; CHECK-NEXT: .LBB2_2:
+; CHECK-NEXT: sarb $4, %al
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: retq
+;
+; CHECK32-LABEL: func3:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %al
+; CHECK32-NEXT: movb {{[0-9]+}}(%esp), %dl
+; CHECK32-NEXT: shlb $4, %dl
+; CHECK32-NEXT: shlb $4, %al
+; CHECK32-NEXT: movl %eax, %ecx
+; CHECK32-NEXT: addb %dl, %cl
+; CHECK32-NEXT: setns %cl
+; CHECK32-NEXT: addb %dl, %al
+; CHECK32-NEXT: jno .LBB2_2
+; CHECK32-NEXT: # %bb.1:
+; CHECK32-NEXT: addb $127, %cl
+; CHECK32-NEXT: movl %ecx, %eax
+; CHECK32-NEXT: .LBB2_2:
+; CHECK32-NEXT: sarb $4, %al
+; CHECK32-NEXT: retl
+ %tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y);
+ ret i4 %tmp;
+}
+
+define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) {
+; CHECK-LABEL: vec:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm1[1,1,2,3]
+; CHECK-NEXT: movd %xmm2, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm0[1,1,2,3]
+; CHECK-NEXT: movd %xmm2, %r8d
+; CHECK-NEXT: xorl %edx, %edx
+; CHECK-NEXT: movl %r8d, %esi
+; CHECK-NEXT: addl %ecx, %esi
+; CHECK-NEXT: setns %dl
+; CHECK-NEXT: addl $2147483647, %edx # imm = 0x7FFFFFFF
+; CHECK-NEXT: addl %ecx, %r8d
+; CHECK-NEXT: cmovol %edx, %r8d
+; CHECK-NEXT: movd %xmm1, %edx
+; CHECK-NEXT: movd %xmm0, %ecx
+; CHECK-NEXT: xorl %esi, %esi
+; CHECK-NEXT: movl %ecx, %edi
+; CHECK-NEXT: addl %edx, %edi
+; CHECK-NEXT: setns %sil
+; CHECK-NEXT: addl $2147483647, %esi # imm = 0x7FFFFFFF
+; CHECK-NEXT: addl %edx, %ecx
+; CHECK-NEXT: cmovol %esi, %ecx
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm1[2,3,0,1]
+; CHECK-NEXT: movd %xmm2, %edx
+; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,0,1]
+; CHECK-NEXT: movd %xmm2, %eax
+; CHECK-NEXT: xorl %edi, %edi
+; CHECK-NEXT: movl %eax, %esi
+; CHECK-NEXT: addl %edx, %esi
+; CHECK-NEXT: setns %dil
+; CHECK-NEXT: addl $2147483647, %edi # imm = 0x7FFFFFFF
+; CHECK-NEXT: addl %edx, %eax
+; CHECK-NEXT: cmovol %edi, %eax
+; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm1[3,1,2,3]
+; CHECK-NEXT: movd %xmm1, %r9d
+; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3]
+; CHECK-NEXT: movd %xmm0, %edx
+; CHECK-NEXT: xorl %edi, %edi
+; CHECK-NEXT: movl %edx, %esi
+; CHECK-NEXT: addl %r9d, %esi
+; CHECK-NEXT: setns %dil
+; CHECK-NEXT: addl $2147483647, %edi # imm = 0x7FFFFFFF
+; CHECK-NEXT: addl %r9d, %edx
+; CHECK-NEXT: cmovol %edi, %edx
+; CHECK-NEXT: movd %edx, %xmm0
+; CHECK-NEXT: movd %eax, %xmm1
+; CHECK-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
+; CHECK-NEXT: movd %ecx, %xmm0
+; CHECK-NEXT: movd %r8d, %xmm2
+; CHECK-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1]
+; CHECK-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
+; CHECK-NEXT: retq
+;
+; CHECK32-LABEL: vec:
+; CHECK32: # %bb.0:
+; CHECK32-NEXT: pushl %ebp
+; CHECK32-NEXT: .cfi_def_cfa_offset 8
+; CHECK32-NEXT: pushl %ebx
+; CHECK32-NEXT: .cfi_def_cfa_offset 12
+; CHECK32-NEXT: pushl %edi
+; CHECK32-NEXT: .cfi_def_cfa_offset 16
+; CHECK32-NEXT: pushl %esi
+; CHECK32-NEXT: .cfi_def_cfa_offset 20
+; CHECK32-NEXT: .cfi_offset %esi, -20
+; CHECK32-NEXT: .cfi_offset %edi, -16
+; CHECK32-NEXT: .cfi_offset %ebx, -12
+; CHECK32-NEXT: .cfi_offset %ebp, -8
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
+; CHECK32-NEXT: xorl %eax, %eax
+; CHECK32-NEXT: movl %ecx, %esi
+; CHECK32-NEXT: addl %edx, %esi
+; CHECK32-NEXT: setns %al
+; CHECK32-NEXT: addl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK32-NEXT: addl %edx, %ecx
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edx
+; CHECK32-NEXT: cmovol %eax, %ecx
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
+; CHECK32-NEXT: xorl %eax, %eax
+; CHECK32-NEXT: movl %edx, %edi
+; CHECK32-NEXT: addl %esi, %edi
+; CHECK32-NEXT: setns %al
+; CHECK32-NEXT: addl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK32-NEXT: addl %esi, %edx
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi
+; CHECK32-NEXT: cmovol %eax, %edx
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edi
+; CHECK32-NEXT: xorl %eax, %eax
+; CHECK32-NEXT: movl %esi, %ebx
+; CHECK32-NEXT: addl %edi, %ebx
+; CHECK32-NEXT: setns %al
+; CHECK32-NEXT: addl $2147483647, %eax # imm = 0x7FFFFFFF
+; CHECK32-NEXT: addl %edi, %esi
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %edi
+; CHECK32-NEXT: cmovol %eax, %esi
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK32-NEXT: xorl %ebx, %ebx
+; CHECK32-NEXT: movl %edi, %ebp
+; CHECK32-NEXT: addl %eax, %ebp
+; CHECK32-NEXT: setns %bl
+; CHECK32-NEXT: addl $2147483647, %ebx # imm = 0x7FFFFFFF
+; CHECK32-NEXT: addl %eax, %edi
+; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %eax
+; CHECK32-NEXT: cmovol %ebx, %edi
+; CHECK32-NEXT: movl %ecx, 12(%eax)
+; CHECK32-NEXT: movl %edx, 8(%eax)
+; CHECK32-NEXT: movl %esi, 4(%eax)
+; CHECK32-NEXT: movl %edi, (%eax)
+; CHECK32-NEXT: popl %esi
+; CHECK32-NEXT: .cfi_def_cfa_offset 16
+; CHECK32-NEXT: popl %edi
+; CHECK32-NEXT: .cfi_def_cfa_offset 12
+; CHECK32-NEXT: popl %ebx
+; CHECK32-NEXT: .cfi_def_cfa_offset 8
+; CHECK32-NEXT: popl %ebp
+; CHECK32-NEXT: .cfi_def_cfa_offset 4
+; CHECK32-NEXT: retl $4
+ %tmp = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y);
+ ret <4 x i32> %tmp;
+}
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