[PATCH] D53235: [RISCV] Add RV64F codegen support
Eli Friedman via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 15 12:14:07 PDT 2018
efriedma added inline comments.
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Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:8959
+ // fold anyext where ToVT==FromVT
+ if (VT == N0->getValueType(N0.getResNo()))
+ return N0;
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Not sure how you're ending up in a situation where this matters; getNode() will normally fold away an ANY_EXTEND where the operand and result have the same type.
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Comment at: lib/Target/RISCV/RISCVISelDAGToDAG.cpp:161
+ }
+ case ISD::AssertSext: {
+ if (!Subtarget->is64Bit())
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The point of this is to try to generate a "narrower" FP_TO_SINT where possible? Does this transform actually improve performance?
================
Comment at: lib/Target/RISCV/RISCVInstrInfoF.td:354
+def : Pat<(RISCVBitcastAndSextF32ToI64 (RISCVTruncAndBitcastI64ToF32 GPR:$src)),
+ (i64 GPR:$src)>;
+
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Maybe better to implement this as a DAGCombine?
https://reviews.llvm.org/D53235
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