[llvm] r344531 - [AArch64] add tests for fmul x, -2.0 with undef elts; NFC

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Mon Oct 15 09:44:00 2018
New Revision: 344531

URL: http://llvm.org/viewvc/llvm-project?rev=344531&view=rev
Log:
[AArch64] add tests for fmul x, -2.0 with undef elts; NFC

Also, add tests with commuted operands. There was no coverage for that case.

Modified:
    llvm/trunk/test/CodeGen/AArch64/fadd-combines.ll

Modified: llvm/trunk/test/CodeGen/AArch64/fadd-combines.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/fadd-combines.ll?rev=344531&r1=344530&r2=344531&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/fadd-combines.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/fadd-combines.ll Mon Oct 15 09:44:00 2018
@@ -51,8 +51,8 @@ define double @test4(double %a, double %
   ret double %add2
 }
 
-define <4 x float> @test5(<4 x float> %a, <4 x float> %b) {
-; CHECK-LABEL: test5:
+define <4 x float> @fmulnegtwo_vec(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: fmulnegtwo_vec:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fadd v1.4s, v1.4s, v1.4s
 ; CHECK-NEXT:    fsub v0.4s, v0.4s, v1.4s
@@ -62,6 +62,41 @@ define <4 x float> @test5(<4 x float> %a
   ret <4 x float> %add
 }
 
+define <4 x float> @fmulnegtwo_vec_commute(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: fmulnegtwo_vec_commute:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    fadd v1.4s, v1.4s, v1.4s
+; CHECK-NEXT:    fsub v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    ret
+  %mul = fmul <4 x float> %b, <float -2.0, float -2.0, float -2.0, float -2.0>
+  %add = fadd <4 x float> %mul, %a
+  ret <4 x float> %add
+}
+
+define <4 x float> @fmulnegtwo_vec_undefs(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: fmulnegtwo_vec_undefs:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v2.4s, #192, lsl #24
+; CHECK-NEXT:    fmul v1.4s, v1.4s, v2.4s
+; CHECK-NEXT:    fadd v0.4s, v0.4s, v1.4s
+; CHECK-NEXT:    ret
+  %mul = fmul <4 x float> %b, <float undef, float -2.0, float undef, float -2.0>
+  %add = fadd <4 x float> %a, %mul
+  ret <4 x float> %add
+}
+
+define <4 x float> @fmulnegtwo_vec_commute_undefs(<4 x float> %a, <4 x float> %b) {
+; CHECK-LABEL: fmulnegtwo_vec_commute_undefs:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    movi v2.4s, #192, lsl #24
+; CHECK-NEXT:    fmul v1.4s, v1.4s, v2.4s
+; CHECK-NEXT:    fadd v0.4s, v1.4s, v0.4s
+; CHECK-NEXT:    ret
+  %mul = fmul <4 x float> %b, <float -2.0, float undef, float -2.0, float -2.0>
+  %add = fadd <4 x float> %mul, %a
+  ret <4 x float> %add
+}
+
 define <4 x float> @test6(<4 x float> %a, <4 x float> %b) {
 ; CHECK-LABEL: test6:
 ; CHECK:       // %bb.0:
@@ -99,10 +134,10 @@ define double @test7(double %a, double %
 define float @fadd_const_multiuse_fmf(float %x) {
 ; CHECK-LABEL: fadd_const_multiuse_fmf:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI7_0
-; CHECK-NEXT:    adrp x9, .LCPI7_1
-; CHECK-NEXT:    ldr s1, [x8, :lo12:.LCPI7_0]
-; CHECK-NEXT:    ldr s2, [x9, :lo12:.LCPI7_1]
+; CHECK-NEXT:    adrp x8, .LCPI10_0
+; CHECK-NEXT:    adrp x9, .LCPI10_1
+; CHECK-NEXT:    ldr s1, [x8, :lo12:.LCPI10_0]
+; CHECK-NEXT:    ldr s2, [x9, :lo12:.LCPI10_1]
 ; CHECK-NEXT:    fadd s1, s0, s1
 ; CHECK-NEXT:    fadd s0, s0, s2
 ; CHECK-NEXT:    fadd s0, s1, s0
@@ -120,10 +155,10 @@ define float @fadd_const_multiuse_fmf(fl
 define float @fadd_const_multiuse_attr(float %x) #0 {
 ; CHECK-LABEL: fadd_const_multiuse_attr:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x9, .LCPI8_1
-; CHECK-NEXT:    adrp x8, .LCPI8_0
-; CHECK-NEXT:    ldr s1, [x9, :lo12:.LCPI8_1]
-; CHECK-NEXT:    ldr s2, [x8, :lo12:.LCPI8_0]
+; CHECK-NEXT:    adrp x9, .LCPI11_1
+; CHECK-NEXT:    adrp x8, .LCPI11_0
+; CHECK-NEXT:    ldr s1, [x9, :lo12:.LCPI11_1]
+; CHECK-NEXT:    ldr s2, [x8, :lo12:.LCPI11_0]
 ; CHECK-NEXT:    fadd s1, s0, s1
 ; CHECK-NEXT:    fadd s1, s2, s1
 ; CHECK-NEXT:    fadd s0, s0, s1