[PATCH] D53268: [X86] WIP: Stop promoting and/or/xor/andn to vXi64.

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

I think this is the right way to go. It's a blob of patterns, but they're stamped out in a regular form.
When the logic ops are promoted, we might have to deal with them separately as noted in https://reviews.llvm.org/D51553.

Can we do something similar to the scalar logic ops to reduce the duplication?

  def NAME#16rr : BinOpRR_F<BaseOpc, mnemonic, Xi16, opnode>;
  def NAME#32rr : BinOpRR_F<BaseOpc, mnemonic, Xi32, opnode>;
  def NAME#64rr : BinOpRR_F<BaseOpc, mnemonic, Xi64, opnode>;


Repository:
  rL LLVM

https://reviews.llvm.org/D53268