[PATCH] D53258: [LegalizeDAG] Add generic vector CTPOP expansion (PR32655) (WIP)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: bruno, craig.topper, efriedma, spatel, t.p.northover, javed.absar.
Herald added a subscriber: kristof.beyls.

This WIP patch adds support for expanding vector CTPOP instructions and removes the x86 'bitmath' lowering which replicates the same expansion.

Several things to note with the current state of this patch:

1 - ARM CTPOP lowering (https://reviews.llvm.org/D53257) needs to be fixed first as ARM doesn't fully custom lower v1i64/v2i64 MUL, relying on expansion for the fully general case and LegalizeDAG can't yet deal with that for vector types.
2 - AARCH64 CTPOP lowering is pretty weak as well and probably needs to match the approach in https://reviews.llvm.org/D53257.
3 - X86 logic instructions are getting stuck between BITCASTs preventing the relevant reassociations/demandedbits code from combining/removing the duplicate AND ops, this is currently being looked at (e.g. https://reviews.llvm.org/D53229).


Repository:
  rL LLVM

https://reviews.llvm.org/D53258

Files:
  lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/AArch64/arm64-vpopcnt.ll
  test/CodeGen/X86/vec_ctbits.ll
  test/CodeGen/X86/vector-lzcnt-128.ll
  test/CodeGen/X86/vector-popcnt-128.ll
  test/CodeGen/X86/vector-tzcnt-128.ll

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