[llvm] r344477 - [LegalizeDAG] Don't bother with final MUL+SRL stage for byte CTPOP.

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Sun Oct 14 08:56:28 2018
New Revision: 344477

URL: http://llvm.org/viewvc/llvm-project?rev=344477&view=rev
Log:
[LegalizeDAG] Don't bother with final MUL+SRL stage for byte CTPOP. 

The final stage of CTPOP expansion (v = (v * 0x01010101...) >> (Len - 8)) is completely pointless for the byte (Len = 8) case as it reduces to (v = (v * 0x01...) >> 0), but annoyingly this doesn't always get optimized away. 

Found while investigating generic vector CTPOP expansion (PR32655).

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=344477&r1=344476&r2=344477&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Sun Oct 14 08:56:28 2018
@@ -2750,9 +2750,10 @@ SDValue SelectionDAGLegalize::ExpandBitC
                                              DAG.getConstant(4, dl, ShVT))),
                      Mask0F);
     // v = (v * 0x01010101...) >> (Len - 8)
-    Op = DAG.getNode(ISD::SRL, dl, VT,
-                     DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
-                     DAG.getConstant(Len - 8, dl, ShVT));
+    if (Len > 8)
+      Op = DAG.getNode(ISD::SRL, dl, VT,
+                       DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
+                       DAG.getConstant(Len - 8, dl, ShVT));
 
     return Op;
   }