[PATCH] D53107: [X86] Move promotion of vector and/or/xor from legalization to DAG combine

[Craig Topper via Phabricator via llvm-commits]

craig.topper updated this revision to Diff 169580.
craig.topper added a comment.

Add a fix to prevent xor+psrl from being selected over andn.


Repository:
  rL LLVM

https://reviews.llvm.org/D53107

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/avx-logic.ll
  test/CodeGen/X86/avx512-ext.ll
  test/CodeGen/X86/avx512-insert-extract.ll
  test/CodeGen/X86/avx512-schedule.ll
  test/CodeGen/X86/avx512vl-vec-masked-cmp.ll
  test/CodeGen/X86/cast-vsel.ll
  test/CodeGen/X86/combine-sdiv.ll
  test/CodeGen/X86/combine-srl.ll
  test/CodeGen/X86/gather-addresses.ll
  test/CodeGen/X86/horizontal-reduce-umax.ll
  test/CodeGen/X86/horizontal-reduce-umin.ll
  test/CodeGen/X86/known-bits.ll
  test/CodeGen/X86/nontemporal-loads.ll
  test/CodeGen/X86/paddus.ll
  test/CodeGen/X86/psubus.ll
  test/CodeGen/X86/sat-add.ll
  test/CodeGen/X86/setcc-lowering.ll
  test/CodeGen/X86/sse2-intrinsics-canonical.ll
  test/CodeGen/X86/unfold-masked-merge-vector-variablemask-const.ll
  test/CodeGen/X86/v8i1-masks.ll
  test/CodeGen/X86/vector-blend.ll
  test/CodeGen/X86/vector-reduce-umax.ll
  test/CodeGen/X86/vector-reduce-umin.ll
  test/CodeGen/X86/vector-shift-lshr-128.ll
  test/CodeGen/X86/vector-shift-shl-128.ll
  test/CodeGen/X86/vector-shuffle-256-v16.ll
  test/CodeGen/X86/vector-trunc-math.ll
  test/CodeGen/X86/vector-trunc-packus.ll
  test/CodeGen/X86/vector-trunc-ssat.ll
  test/CodeGen/X86/vector-trunc-usat.ll
  test/CodeGen/X86/vector-trunc.ll
  test/CodeGen/X86/vshift-6.ll
  test/CodeGen/X86/x86-interleaved-access.ll

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