[PATCH] D53237: [RISCV] Implement RV64D codegen

[Alex Bradbury via Phabricator via llvm-commits]

asb created this revision.
asb added reviewers: apazos, sabuasal.
Herald added subscribers: jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, mgrang, edward-jones, zzheng, shiva0217, kito-cheng, niosHD, simoncook, johnrusso, rbar, qcolombet.

Compared to RV64F, supporting RV64D is very straight-forward. This patch introduces the necessary instruction patterns, as well as adding support to the custom selection code for catching producing double-precision FCVT.


https://reviews.llvm.org/D53237

Files:
  lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVInstrInfoD.td
  test/CodeGen/RISCV/double-arith.ll
  test/CodeGen/RISCV/double-br-fcmp.ll
  test/CodeGen/RISCV/double-convert.ll
  test/CodeGen/RISCV/double-fcmp.ll
  test/CodeGen/RISCV/double-imm.ll
  test/CodeGen/RISCV/double-intrinsics.ll
  test/CodeGen/RISCV/double-mem.ll
  test/CodeGen/RISCV/double-select-fcmp.ll
  test/CodeGen/RISCV/double-stack-spill-restore.ll

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