[llvm] r344422 - [LegalizeVectorTypes] When widening the result of a bitcast from a scalar type, use a scalar_to_vector to turn the scalar into a vector intead of a build vector full of mostly undefs.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 12 14:59:55 PDT 2018
Author: ctopper
Date: Fri Oct 12 14:59:55 2018
New Revision: 344422
URL: http://llvm.org/viewvc/llvm-project?rev=344422&view=rev
Log:
[LegalizeVectorTypes] When widening the result of a bitcast from a scalar type, use a scalar_to_vector to turn the scalar into a vector intead of a build vector full of mostly undefs.
This is more consistent with what we usually do and matches some code X86 custom emits in some cases that I think I can cleanup.
The MIPS test change just looks to be an instruction ordering change.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/trunk/test/CodeGen/Mips/cconv/vector.ll
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=344422&r1=344421&r2=344422&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Fri Oct 12 14:59:55 2018
@@ -3022,22 +3022,20 @@ SDValue DAGTypeLegalizer::WidenVecRes_BI
}
if (TLI.isTypeLegal(NewInVT)) {
- // Because the result and the input are different vector types, widening
- // the result could create a legal type but widening the input might make
- // it an illegal type that might lead to repeatedly splitting the input
- // and then widening it. To avoid this, we widen the input only if
- // it results in a legal type.
- SmallVector<SDValue, 16> Ops(NewNumElts);
- SDValue UndefVal = DAG.getUNDEF(InVT);
- Ops[0] = InOp;
- for (unsigned i = 1; i < NewNumElts; ++i)
- Ops[i] = UndefVal;
-
SDValue NewVec;
- if (InVT.isVector())
+ if (InVT.isVector()) {
+ // Because the result and the input are different vector types, widening
+ // the result could create a legal type but widening the input might make
+ // it an illegal type that might lead to repeatedly splitting the input
+ // and then widening it. To avoid this, we widen the input only if
+ // it results in a legal type.
+ SmallVector<SDValue, 16> Ops(NewNumElts, DAG.getUNDEF(InVT));
+ Ops[0] = InOp;
+
NewVec = DAG.getNode(ISD::CONCAT_VECTORS, dl, NewInVT, Ops);
- else
- NewVec = DAG.getBuildVector(NewInVT, dl, Ops);
+ } else {
+ NewVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewInVT, InOp);
+ }
return DAG.getNode(ISD::BITCAST, dl, WidenVT, NewVec);
}
}
Modified: llvm/trunk/test/CodeGen/Mips/cconv/vector.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/cconv/vector.ll?rev=344422&r1=344421&r2=344422&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/cconv/vector.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/cconv/vector.ll Fri Oct 12 14:59:55 2018
@@ -2420,10 +2420,10 @@ define void @float_2(<2 x float> %a, <2
; MIPS64R5EB-NEXT: lui $1, %hi(%neg(%gp_rel(float_2)))
; MIPS64R5EB-NEXT: daddu $1, $1, $25
; MIPS64R5EB-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(float_2)))
-; MIPS64R5EB-NEXT: sd $5, 0($sp)
-; MIPS64R5EB-NEXT: sd $4, 16($sp)
-; MIPS64R5EB-NEXT: ld.w $w0, 0($sp)
-; MIPS64R5EB-NEXT: ld.w $w1, 16($sp)
+; MIPS64R5EB-NEXT: sd $5, 16($sp)
+; MIPS64R5EB-NEXT: sd $4, 0($sp)
+; MIPS64R5EB-NEXT: ld.w $w0, 16($sp)
+; MIPS64R5EB-NEXT: ld.w $w1, 0($sp)
; MIPS64R5EB-NEXT: fadd.w $w0, $w1, $w0
; MIPS64R5EB-NEXT: shf.w $w0, $w0, 177
; MIPS64R5EB-NEXT: copy_s.d $2, $w0[0]
@@ -2463,10 +2463,10 @@ define void @float_2(<2 x float> %a, <2
; MIPS64R5EL-NEXT: lui $1, %hi(%neg(%gp_rel(float_2)))
; MIPS64R5EL-NEXT: daddu $1, $1, $25
; MIPS64R5EL-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(float_2)))
-; MIPS64R5EL-NEXT: sd $5, 0($sp)
-; MIPS64R5EL-NEXT: sd $4, 16($sp)
-; MIPS64R5EL-NEXT: ld.w $w0, 0($sp)
-; MIPS64R5EL-NEXT: ld.w $w1, 16($sp)
+; MIPS64R5EL-NEXT: sd $5, 16($sp)
+; MIPS64R5EL-NEXT: sd $4, 0($sp)
+; MIPS64R5EL-NEXT: ld.w $w0, 16($sp)
+; MIPS64R5EL-NEXT: ld.w $w1, 0($sp)
; MIPS64R5EL-NEXT: fadd.w $w0, $w1, $w0
; MIPS64R5EL-NEXT: copy_s.d $2, $w0[0]
; MIPS64R5EL-NEXT: ld $1, %got_disp(float_res_v2f32)($1)
@@ -6211,14 +6211,14 @@ define float @mixed_i8(<2 x float> %a, i
; MIPS64R5-NEXT: andi $1, $1, 255
; MIPS64R5-NEXT: sw $1, 36($sp)
; MIPS64R5-NEXT: sw $1, 32($sp)
-; MIPS64R5-NEXT: sd $4, 16($sp)
+; MIPS64R5-NEXT: sd $4, 0($sp)
; MIPS64R5-NEXT: ld.w $w0, 32($sp)
; MIPS64R5-NEXT: ffint_s.w $w0, $w0
-; MIPS64R5-NEXT: ld.w $w1, 16($sp)
-; MIPS64R5-NEXT: fadd.w $w0, $w0, $w1
-; MIPS64R5-NEXT: sd $6, 0($sp)
; MIPS64R5-NEXT: ld.w $w1, 0($sp)
; MIPS64R5-NEXT: fadd.w $w0, $w0, $w1
+; MIPS64R5-NEXT: sd $6, 16($sp)
+; MIPS64R5-NEXT: ld.w $w1, 16($sp)
+; MIPS64R5-NEXT: fadd.w $w0, $w0, $w1
; MIPS64R5-NEXT: splati.w $w1, $w0[1]
; MIPS64R5-NEXT: add.s $f0, $f0, $f1
; MIPS64R5-NEXT: daddiu $sp, $sp, 48
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