[PATCH] D53201: [DAGCombiner] reduce insert+bitcast+extract vector ops to truncate (PR39016)

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: RKSimon, craig.topper, lebedev.ri, efriedma.
Herald added a subscriber: mcrosier.
Herald added a reviewer: javed.absar.

This is a late backend subset of the IR transform added with:
https://reviews.llvm.org/D52439

We can confirm that the conversion to a 'trunc' is correct by running:
$ opt -instcombine -data-layout="e"
(assuming the IR transforms are correct; change "e" to "E" for big-endian)

As discussed in PR39016:
https://bugs.llvm.org/show_bug.cgi?id=39016
...the pattern may emerge during legalization, so that's why I've opted to wait for an insertelement to become a scalar_to_vector in the pattern matching here.

The DAG allows for fun variations that are not possible in IR. Result types for extracts and scalar_to_vector don't necessarily match input types, so that means we have to be a bit more careful in the transform (see code comments).

The tests show that we don't handle cases that require a shift (as we did in the IR version). I've left that as a potential follow-up because I'm not sure if that's a real concern at this late stage.

The bug report mentions an x86 regression test that isn't changed here, so I'm also not sure if this is enough to close the bug report.


https://reviews.llvm.org/D53201

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/AArch64/extract-insert.ll
  test/CodeGen/X86/extract-insert.ll
  test/CodeGen/X86/mmx-coalescing.ll

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