[PATCH] D53053: [Intrinsic] Signed Saturation Addition Intrinsic

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

Are we not supporting vectors at all? That needs to be checked in the IR verifier if so. Though I would really like to see this for vectors since X86 has 8 and 16 bit saturating vector addition.



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Comment at: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:554
+  EVT PromotedType = Op1Promoted.getValueType();
+  unsigned NewBits = Op1Promoted.getValueSizeInBits();
+  unsigned SHLAmount = NewBits - OldBits;
----------------
What about vector types?


Repository:
  rL LLVM

https://reviews.llvm.org/D53053