[PATCH] D51828: [RISCV] Fix disassembling of fence instruction with invalid field

[Ana Pazos via Phabricator via llvm-commits]

This revision was not accepted when it landed; it landed in state "Needs Review".
This revision was automatically updated to reflect the committed changes.
Closed by commit rL344309: [RISCV] Fix disassembling of fence instruction with invalid field (authored by apazos, committed by ).
Herald added subscribers: llvm-commits, jrtc27.

Changed prior to commit:
  https://reviews.llvm.org/D51828?vs=169322&id=169328#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D51828

Files:
  llvm/trunk/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp
  llvm/trunk/test/MC/Disassembler/RISCV/unknown-fence-field.txt
  llvm/trunk/test/MC/RISCV/rv32i-invalid.s


Index: llvm/trunk/test/MC/RISCV/rv32i-invalid.s
===================================================================
--- llvm/trunk/test/MC/RISCV/rv32i-invalid.s
+++ llvm/trunk/test/MC/RISCV/rv32i-invalid.s
@@ -6,6 +6,7 @@
 fence wr, wr # CHECK: :[[@LINE]]:7: error: operand must be formed of letters selected in-order from 'iorw'
 fence rw, rr # CHECK: :[[@LINE]]:11: error: operand must be formed of letters selected in-order from 'iorw'
 fence 1, rw # CHECK: :[[@LINE]]:7: error: operand must be formed of letters selected in-order from 'iorw'
+fence unknown, unknown # CHECK: :[[@LINE]]:7: error: operand must be formed of letters selected in-order from 'iorw'
 
 ## uimm5
 slli a0, a0, 32 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31]
Index: llvm/trunk/test/MC/Disassembler/RISCV/unknown-fence-field.txt
===================================================================
--- llvm/trunk/test/MC/Disassembler/RISCV/unknown-fence-field.txt
+++ llvm/trunk/test/MC/Disassembler/RISCV/unknown-fence-field.txt
@@ -0,0 +1,9 @@
+# RUN: llvm-mc -disassemble -triple=riscv32 < %s 2>&1 | FileCheck %s
+# RUN: llvm-mc -disassemble -triple=riscv64 < %s 2>&1 | FileCheck %s
+#
+# Test generated by a LLVM MC Disassembler Protocol Buffer Fuzzer
+# for the RISC-V assembly language.
+
+# This decodes as fence , iorw with invalid fence field as 0.
+[0x0f 0x00 0xf0 0x00]
+# CHECK: fence unknown, iorw
Index: llvm/trunk/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp
===================================================================
--- llvm/trunk/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp
+++ llvm/trunk/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp
@@ -93,14 +93,18 @@
                                      const MCSubtargetInfo &STI,
                                      raw_ostream &O) {
   unsigned FenceArg = MI->getOperand(OpNo).getImm();
+  assert (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg");
+
   if ((FenceArg & RISCVFenceField::I) != 0)
     O << 'i';
   if ((FenceArg & RISCVFenceField::O) != 0)
     O << 'o';
   if ((FenceArg & RISCVFenceField::R) != 0)
     O << 'r';
   if ((FenceArg & RISCVFenceField::W) != 0)
     O << 'w';
+  if (FenceArg == 0)
+    O << "unknown";
 }
 
 void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo,


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