[PATCH] D53144: [MachineCSE][GlobalISel] Making sure MachineCSE works mid-GlobalISel (again)

[Roman Tereshin via Phabricator via llvm-commits]

rtereshin created this revision.
rtereshin added a reviewer: aditya_nandakumar.
Herald added subscribers: llvm-commits, kristof.beyls, rovka.
Herald added a reviewer: javed.absar.

Change of approach, it looks like it's much better idea to deal with the
vregs that have LLTs and reg classes both properly, than trying to
avoid creating those across all GlobalISel passes and all targets.


Repository:
  rL LLVM

https://reviews.llvm.org/D53144

Files:
  include/llvm/CodeGen/MachineRegisterInfo.h
  lib/CodeGen/MachineCSE.cpp
  lib/CodeGen/MachineRegisterInfo.cpp
  test/CodeGen/AArch64/GlobalISel/machine-cse-mid-pipeline.mir

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