[llvm] r344238 - [RISCV] Re-generate test/CodeGen/RISCV/vararg.ll after r344142
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Thu Oct 11 04:11:58 PDT 2018
Author: asb
Date: Thu Oct 11 04:11:58 2018
New Revision: 344238
URL: http://llvm.org/viewvc/llvm-project?rev=344238&view=rev
Log:
[RISCV] Re-generate test/CodeGen/RISCV/vararg.ll after r344142
The improved load-store forwarding committed in r344142 broke this test.
Modified:
llvm/trunk/test/CodeGen/RISCV/vararg.ll
Modified: llvm/trunk/test/CodeGen/RISCV/vararg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/vararg.ll?rev=344238&r1=344237&r2=344238&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/vararg.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/vararg.ll Thu Oct 11 04:11:58 2018
@@ -17,16 +17,16 @@ define i32 @va1(i8* %fmt, ...) nounwind
; RV32I-FPELIM-LABEL: va1:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -48
-; RV32I-FPELIM-NEXT: sw a1, 20(sp)
+; RV32I-FPELIM-NEXT: mv a0, a1
; RV32I-FPELIM-NEXT: sw a7, 44(sp)
; RV32I-FPELIM-NEXT: sw a6, 40(sp)
; RV32I-FPELIM-NEXT: sw a5, 36(sp)
; RV32I-FPELIM-NEXT: sw a4, 32(sp)
; RV32I-FPELIM-NEXT: sw a3, 28(sp)
; RV32I-FPELIM-NEXT: sw a2, 24(sp)
-; RV32I-FPELIM-NEXT: addi a0, sp, 24
-; RV32I-FPELIM-NEXT: sw a0, 12(sp)
-; RV32I-FPELIM-NEXT: lw a0, 20(sp)
+; RV32I-FPELIM-NEXT: addi a1, sp, 24
+; RV32I-FPELIM-NEXT: sw a1, 12(sp)
+; RV32I-FPELIM-NEXT: sw a0, 20(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 48
; RV32I-FPELIM-NEXT: ret
;
@@ -36,16 +36,16 @@ define i32 @va1(i8* %fmt, ...) nounwind
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
-; RV32I-WITHFP-NEXT: sw a1, 4(s0)
+; RV32I-WITHFP-NEXT: mv a0, a1
; RV32I-WITHFP-NEXT: sw a7, 28(s0)
; RV32I-WITHFP-NEXT: sw a6, 24(s0)
; RV32I-WITHFP-NEXT: sw a5, 20(s0)
; RV32I-WITHFP-NEXT: sw a4, 16(s0)
; RV32I-WITHFP-NEXT: sw a3, 12(s0)
; RV32I-WITHFP-NEXT: sw a2, 8(s0)
-; RV32I-WITHFP-NEXT: addi a0, s0, 8
-; RV32I-WITHFP-NEXT: sw a0, -12(s0)
-; RV32I-WITHFP-NEXT: lw a0, 4(s0)
+; RV32I-WITHFP-NEXT: addi a1, s0, 8
+; RV32I-WITHFP-NEXT: sw a1, -12(s0)
+; RV32I-WITHFP-NEXT: sw a0, 4(s0)
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 48
@@ -66,16 +66,16 @@ define i32 @va1_va_arg(i8* %fmt, ...) no
; RV32I-FPELIM-LABEL: va1_va_arg:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -48
-; RV32I-FPELIM-NEXT: sw a1, 20(sp)
+; RV32I-FPELIM-NEXT: mv a0, a1
; RV32I-FPELIM-NEXT: sw a7, 44(sp)
; RV32I-FPELIM-NEXT: sw a6, 40(sp)
; RV32I-FPELIM-NEXT: sw a5, 36(sp)
; RV32I-FPELIM-NEXT: sw a4, 32(sp)
; RV32I-FPELIM-NEXT: sw a3, 28(sp)
; RV32I-FPELIM-NEXT: sw a2, 24(sp)
-; RV32I-FPELIM-NEXT: addi a0, sp, 24
-; RV32I-FPELIM-NEXT: sw a0, 12(sp)
-; RV32I-FPELIM-NEXT: lw a0, 20(sp)
+; RV32I-FPELIM-NEXT: addi a1, sp, 24
+; RV32I-FPELIM-NEXT: sw a1, 12(sp)
+; RV32I-FPELIM-NEXT: sw a0, 20(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 48
; RV32I-FPELIM-NEXT: ret
;
@@ -85,16 +85,16 @@ define i32 @va1_va_arg(i8* %fmt, ...) no
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
-; RV32I-WITHFP-NEXT: sw a1, 4(s0)
+; RV32I-WITHFP-NEXT: mv a0, a1
; RV32I-WITHFP-NEXT: sw a7, 28(s0)
; RV32I-WITHFP-NEXT: sw a6, 24(s0)
; RV32I-WITHFP-NEXT: sw a5, 20(s0)
; RV32I-WITHFP-NEXT: sw a4, 16(s0)
; RV32I-WITHFP-NEXT: sw a3, 12(s0)
; RV32I-WITHFP-NEXT: sw a2, 8(s0)
-; RV32I-WITHFP-NEXT: addi a0, s0, 8
-; RV32I-WITHFP-NEXT: sw a0, -12(s0)
-; RV32I-WITHFP-NEXT: lw a0, 4(s0)
+; RV32I-WITHFP-NEXT: addi a1, s0, 8
+; RV32I-WITHFP-NEXT: sw a1, -12(s0)
+; RV32I-WITHFP-NEXT: sw a0, 4(s0)
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 48
@@ -117,7 +117,7 @@ define i32 @va1_va_arg_alloca(i8* %fmt,
; RV32I-FPELIM-NEXT: sw s0, 8(sp)
; RV32I-FPELIM-NEXT: sw s1, 4(sp)
; RV32I-FPELIM-NEXT: addi s0, sp, 16
-; RV32I-FPELIM-NEXT: sw a1, 4(s0)
+; RV32I-FPELIM-NEXT: mv s1, a1
; RV32I-FPELIM-NEXT: sw a7, 28(s0)
; RV32I-FPELIM-NEXT: sw a6, 24(s0)
; RV32I-FPELIM-NEXT: sw a5, 20(s0)
@@ -126,8 +126,8 @@ define i32 @va1_va_arg_alloca(i8* %fmt,
; RV32I-FPELIM-NEXT: sw a2, 8(s0)
; RV32I-FPELIM-NEXT: addi a0, s0, 8
; RV32I-FPELIM-NEXT: sw a0, -16(s0)
-; RV32I-FPELIM-NEXT: lw s1, 4(s0)
-; RV32I-FPELIM-NEXT: addi a0, s1, 15
+; RV32I-FPELIM-NEXT: sw a1, 4(s0)
+; RV32I-FPELIM-NEXT: addi a0, a1, 15
; RV32I-FPELIM-NEXT: andi a0, a0, -16
; RV32I-FPELIM-NEXT: sub a0, sp, a0
; RV32I-FPELIM-NEXT: mv sp, a0
@@ -147,7 +147,7 @@ define i32 @va1_va_arg_alloca(i8* %fmt,
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: sw s1, 4(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
-; RV32I-WITHFP-NEXT: sw a1, 4(s0)
+; RV32I-WITHFP-NEXT: mv s1, a1
; RV32I-WITHFP-NEXT: sw a7, 28(s0)
; RV32I-WITHFP-NEXT: sw a6, 24(s0)
; RV32I-WITHFP-NEXT: sw a5, 20(s0)
@@ -156,8 +156,8 @@ define i32 @va1_va_arg_alloca(i8* %fmt,
; RV32I-WITHFP-NEXT: sw a2, 8(s0)
; RV32I-WITHFP-NEXT: addi a0, s0, 8
; RV32I-WITHFP-NEXT: sw a0, -16(s0)
-; RV32I-WITHFP-NEXT: lw s1, 4(s0)
-; RV32I-WITHFP-NEXT: addi a0, s1, 15
+; RV32I-WITHFP-NEXT: sw a1, 4(s0)
+; RV32I-WITHFP-NEXT: addi a0, a1, 15
; RV32I-WITHFP-NEXT: andi a0, a0, -16
; RV32I-WITHFP-NEXT: sub a0, sp, a0
; RV32I-WITHFP-NEXT: mv sp, a0
@@ -535,17 +535,17 @@ define i32 @va4_va_copy(i32 %argno, ...)
; RV32I-FPELIM-NEXT: addi sp, sp, -48
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
; RV32I-FPELIM-NEXT: sw s1, 8(sp)
-; RV32I-FPELIM-NEXT: sw a1, 20(sp)
+; RV32I-FPELIM-NEXT: mv s1, a1
; RV32I-FPELIM-NEXT: sw a7, 44(sp)
; RV32I-FPELIM-NEXT: sw a6, 40(sp)
; RV32I-FPELIM-NEXT: sw a5, 36(sp)
; RV32I-FPELIM-NEXT: sw a4, 32(sp)
; RV32I-FPELIM-NEXT: sw a3, 28(sp)
; RV32I-FPELIM-NEXT: sw a2, 24(sp)
+; RV32I-FPELIM-NEXT: sw a1, 20(sp)
; RV32I-FPELIM-NEXT: addi a0, sp, 24
; RV32I-FPELIM-NEXT: sw a0, 4(sp)
; RV32I-FPELIM-NEXT: sw a0, 0(sp)
-; RV32I-FPELIM-NEXT: lw s1, 20(sp)
; RV32I-FPELIM-NEXT: call notdead
; RV32I-FPELIM-NEXT: lw a0, 4(sp)
; RV32I-FPELIM-NEXT: addi a0, a0, 3
@@ -578,17 +578,17 @@ define i32 @va4_va_copy(i32 %argno, ...)
; RV32I-WITHFP-NEXT: sw s0, 24(sp)
; RV32I-WITHFP-NEXT: sw s1, 20(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 32
-; RV32I-WITHFP-NEXT: sw a1, 4(s0)
+; RV32I-WITHFP-NEXT: mv s1, a1
; RV32I-WITHFP-NEXT: sw a7, 28(s0)
; RV32I-WITHFP-NEXT: sw a6, 24(s0)
; RV32I-WITHFP-NEXT: sw a5, 20(s0)
; RV32I-WITHFP-NEXT: sw a4, 16(s0)
; RV32I-WITHFP-NEXT: sw a3, 12(s0)
; RV32I-WITHFP-NEXT: sw a2, 8(s0)
+; RV32I-WITHFP-NEXT: sw a1, 4(s0)
; RV32I-WITHFP-NEXT: addi a0, s0, 8
; RV32I-WITHFP-NEXT: sw a0, -16(s0)
; RV32I-WITHFP-NEXT: sw a0, -20(s0)
-; RV32I-WITHFP-NEXT: lw s1, 4(s0)
; RV32I-WITHFP-NEXT: call notdead
; RV32I-WITHFP-NEXT: lw a0, -16(s0)
; RV32I-WITHFP-NEXT: addi a0, a0, 3
@@ -777,7 +777,6 @@ define i32 @va6_no_fixed_args(...) nounw
; RV32I-FPELIM-LABEL: va6_no_fixed_args:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -48
-; RV32I-FPELIM-NEXT: sw a0, 16(sp)
; RV32I-FPELIM-NEXT: sw a7, 44(sp)
; RV32I-FPELIM-NEXT: sw a6, 40(sp)
; RV32I-FPELIM-NEXT: sw a5, 36(sp)
@@ -785,9 +784,9 @@ define i32 @va6_no_fixed_args(...) nounw
; RV32I-FPELIM-NEXT: sw a3, 28(sp)
; RV32I-FPELIM-NEXT: sw a2, 24(sp)
; RV32I-FPELIM-NEXT: sw a1, 20(sp)
-; RV32I-FPELIM-NEXT: addi a0, sp, 20
-; RV32I-FPELIM-NEXT: sw a0, 12(sp)
-; RV32I-FPELIM-NEXT: lw a0, 16(sp)
+; RV32I-FPELIM-NEXT: addi a1, sp, 20
+; RV32I-FPELIM-NEXT: sw a1, 12(sp)
+; RV32I-FPELIM-NEXT: sw a0, 16(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 48
; RV32I-FPELIM-NEXT: ret
;
@@ -797,7 +796,6 @@ define i32 @va6_no_fixed_args(...) nounw
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
-; RV32I-WITHFP-NEXT: sw a0, 0(s0)
; RV32I-WITHFP-NEXT: sw a7, 28(s0)
; RV32I-WITHFP-NEXT: sw a6, 24(s0)
; RV32I-WITHFP-NEXT: sw a5, 20(s0)
@@ -805,9 +803,9 @@ define i32 @va6_no_fixed_args(...) nounw
; RV32I-WITHFP-NEXT: sw a3, 12(s0)
; RV32I-WITHFP-NEXT: sw a2, 8(s0)
; RV32I-WITHFP-NEXT: sw a1, 4(s0)
-; RV32I-WITHFP-NEXT: addi a0, s0, 4
-; RV32I-WITHFP-NEXT: sw a0, -12(s0)
-; RV32I-WITHFP-NEXT: lw a0, 0(s0)
+; RV32I-WITHFP-NEXT: addi a1, s0, 4
+; RV32I-WITHFP-NEXT: sw a1, -12(s0)
+; RV32I-WITHFP-NEXT: sw a0, 0(s0)
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 48
More information about the llvm-commits
mailing list