[PATCH] D53107: [X86] Move promotion of vector and/or/xor from legalization to DAG combine

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: test/CodeGen/X86/vector-trunc-usat.ll:734
+; SSE2-NEXT:    pxor %xmm4, %xmm2
+; SSE2-NEXT:    psrld $16, %xmm2
+; SSE2-NEXT:    por %xmm1, %xmm2
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Looks like we're now using a pcmpeq+xor+shr instead of a andn with a constant pool throughout this test. I wonder if this already happens with vXi64 types and now it happens with other vector types.


https://reviews.llvm.org/D53107