[PATCH] D53080: [X86] X86ISelLowering: combineAndIntoBEXTR(): support shifted mask.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: test/CodeGen/X86/extract-bits.ll:5843
+; X64-BMI1NOTBM:       # %bb.0:
+; X64-BMI1NOTBM-NEXT:    movl $2579, %eax # imm = 0xA13
+; X64-BMI1NOTBM-NEXT:    bextrl %eax, %edi, %eax
----------------
In a placement that isn't register constrained where the "mov %edi, %eax" copy in the original code doesn't need to exist, isn't this code worse?

For example I would expect this to from 3 instructions to 4 with this patch.
```
define void @foo(i32 %arg, i32* %ptr) {
  %tmp0 = lshr i32 %arg, 19
  %tmp1 = and i32 %tmp0, 1023
  %tmp2 = shl i32 %tmp1, 2
  store i32 %tmp2, i32* %ptr
  ret void
}
```


Repository:
  rL LLVM

https://reviews.llvm.org/D53080