[PATCH] D53095: [x86] add and use fast horizontal vector math subtarget feature

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: craig.topper, andreadb, lebedev.ri, RKSimon, dyung.
Herald added a subscriber: mcrosier.

This is the planned follow-up to https://reviews.llvm.org/D52997. Here we are reducing horizontal vector math codegen by default. AMD Jaguar (btver2) should have no difference with this patch because it has fast-hops. (If we want to set that bit for other CPUs, let me know.)

The code changes are small, but there are many test diffs. For files that are specifically testing for hops, I added RUNs to distinguish fast/slow, so we can see the consequences side-by-side. For files that are primarily concerned with codegen other than hops, I just updated the CHECK lines to reflect the new default codegen.

To recap the recent horizontal op story:

1. Before https://reviews.llvm.org/rL343727, we were producing hops for all subtargets for a variety of patterns. Hops were likely not optimal for all targets though.
2. The IR improvement in r343727 exposed a hole in the backend hop pattern matching, so we reduced hop codegen for all subtargets. That was bad for Jaguar (PR39195).
3. We restored the hop codegen for all targets with https://reviews.llvm.org/rL344141. Good for Jaguar, but probably bad for other CPUs.
4. This patch allows us to distinguish when we want to produce hops, so everyone can be happy. I'm not sure if we have the best predicate here, but the intent is to undo the extra hop-iness that was enabled by r344141.


https://reviews.llvm.org/D53095

Files:
  lib/Target/X86/X86.td
  lib/Target/X86/X86ISelLowering.cpp
  lib/Target/X86/X86Subtarget.h
  test/CodeGen/X86/avx2-phaddsub.ll
  test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
  test/CodeGen/X86/haddsub-shuf.ll
  test/CodeGen/X86/haddsub-undef.ll
  test/CodeGen/X86/haddsub.ll
  test/CodeGen/X86/madd.ll
  test/CodeGen/X86/phaddsub.ll
  test/CodeGen/X86/required-vector-width.ll
  test/CodeGen/X86/sad.ll
  test/CodeGen/X86/vector-reduce-add.ll
  test/CodeGen/X86/vector-reduce-fadd-fast.ll
  test/CodeGen/X86/vector-shuffle-combining.ll

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