[PATCH] D53093: [WebAssembly] Make SIMD instrs def arguments like other instructions

Thomas Lively via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Oct 10 10:24:06 PDT 2018


tlively created this revision.
tlively added a reviewer: aheejin.
Herald added subscribers: llvm-commits, sunfish, jgravelle-google, sbc100, dschuff.

I don't know what this is for or how to test it, but all the
other instructions have it and it was lost for most SIMD instructions
in the reorganization of https://reviews.llvm.org/D53045.


Repository:
  rL LLVM

https://reviews.llvm.org/D53093

Files:
  lib/Target/WebAssembly/WebAssemblyInstrSIMD.td


Index: lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
===================================================================
--- lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
+++ lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
@@ -16,6 +16,7 @@
 multiclass SIMD_I<dag oops_r, dag iops_r, dag oops_s, dag iops_s,
                   list<dag> pattern_r, string asmstr_r = "",
                   string asmstr_s = "", bits<32> simdop = -1> {
+  let Defs = [ARGUMENTS] in
   defm "" : I<oops_r, iops_r, oops_s, iops_s, pattern_r, asmstr_r, asmstr_s,
               !or(0xfd00, !and(0xff, simdop))>,
             Requires<[HasSIMD128]>;
@@ -55,7 +56,6 @@
                                   "v128.const\t"#args, 0>;
 }
 
-let Defs = [ARGUMENTS] in {
 defm "" : ConstVec<v16i8,
                    (ins vec_i8imm_op:$i0, vec_i8imm_op:$i1,
                         vec_i8imm_op:$i2, vec_i8imm_op:$i3,
@@ -100,7 +100,6 @@
                   (ins f64imm_op:$i0, f64imm_op:$i1),
                   (build_vector (f64 fpimm:$i0), (f64 fpimm:$i1)),
                   "$i0, $i1">;
-} // Defs = [ARGUMENTS]
 
 // Create vector with identical lanes: splat
 def splat2 : PatFrag<(ops node:$x), (build_vector node:$x, node:$x)>;


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