[PATCH] D53026: [TargetLowering] Add root node back to work list after successful SimplifyDemandedBits/SimplifyDemandedVectorElts
Simon Pilgrim via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 10 03:46:24 PDT 2018
This revision was automatically updated to reflect the committed changes.
Closed by commit rL344132: [TargetLowering] Add root node back to work list after successful… (authored by RKSimon, committed by ).
Changed prior to commit:
https://reviews.llvm.org/D53026?vs=168818&id=168972#toc
Repository:
rL LLVM
https://reviews.llvm.org/D53026
Files:
llvm/trunk/include/llvm/CodeGen/TargetLowering.h
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Index: llvm/trunk/include/llvm/CodeGen/TargetLowering.h
===================================================================
--- llvm/trunk/include/llvm/CodeGen/TargetLowering.h
+++ llvm/trunk/include/llvm/CodeGen/TargetLowering.h
@@ -2846,7 +2846,8 @@
unsigned Depth = 0,
bool AssumeSingleUse = false) const;
- /// Helper wrapper around SimplifyDemandedBits
+ /// Helper wrapper around SimplifyDemandedBits.
+ /// Adds Op back to the worklist upon success.
bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
DAGCombinerInfo &DCI) const;
@@ -2869,7 +2870,8 @@
TargetLoweringOpt &TLO, unsigned Depth = 0,
bool AssumeSingleUse = false) const;
- /// Helper wrapper around SimplifyDemandedVectorElts
+ /// Helper wrapper around SimplifyDemandedVectorElts.
+ /// Adds Op back to the worklist upon success.
bool SimplifyDemandedVectorElts(SDValue Op, const APInt &DemandedElts,
APInt &KnownUndef, APInt &KnownZero,
DAGCombinerInfo &DCI) const;
Index: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
@@ -36534,16 +36534,10 @@
// simplify ops leading up to it. We only demand the MSB of each lane.
SDValue Mask = Mst->getMask();
if (Mask.getScalarValueSizeInBits() != 1) {
- TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
- !DCI.isBeforeLegalizeOps());
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
APInt DemandedMask(APInt::getSignMask(VT.getScalarSizeInBits()));
- KnownBits Known;
- if (TLI.SimplifyDemandedBits(Mask, DemandedMask, Known, TLO)) {
- DCI.AddToWorklist(Mask.getNode());
- DCI.CommitTargetLoweringOpt(TLO);
+ if (TLI.SimplifyDemandedBits(Mask, DemandedMask, DCI))
return SDValue(N, 0);
- }
}
// TODO: AVX512 targets should also be able to simplify something like the
@@ -38962,16 +38956,10 @@
// With AVX2 we only demand the upper bit of the mask.
if (!Subtarget.hasAVX512()) {
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
- TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
- !DCI.isBeforeLegalizeOps());
SDValue Mask = N->getOperand(2);
- KnownBits Known;
APInt DemandedMask(APInt::getSignMask(Mask.getScalarValueSizeInBits()));
- if (TLI.SimplifyDemandedBits(Mask, DemandedMask, Known, TLO)) {
- DCI.AddToWorklist(Mask.getNode());
- DCI.CommitTargetLoweringOpt(TLO);
+ if (TLI.SimplifyDemandedBits(Mask, DemandedMask, DCI))
return SDValue(N, 0);
- }
}
return SDValue();
Index: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -490,8 +490,10 @@
KnownBits Known;
bool Simplified = SimplifyDemandedBits(Op, DemandedMask, Known, TLO);
- if (Simplified)
+ if (Simplified) {
+ DCI.AddToWorklist(Op.getNode());
DCI.CommitTargetLoweringOpt(TLO);
+ }
return Simplified;
}
@@ -1359,8 +1361,10 @@
bool Simplified =
SimplifyDemandedVectorElts(Op, DemandedElts, KnownUndef, KnownZero, TLO);
- if (Simplified)
+ if (Simplified) {
+ DCI.AddToWorklist(Op.getNode());
DCI.CommitTargetLoweringOpt(TLO);
+ }
return Simplified;
}
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