[PATCH] D53055: [MCA] Limit the number of bytes fetched per cycle.

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

This should eventually be configurable in the sched target, right?
Also, a single fetch 'queue' also may not fully fit everyone.
https://www.amd.com/system/files/TechDocs/47414_15h_sw_opt_guide.pdf

> While previous AMD64 family 15h processors had a single 32-byte fetch window, AMD Family 15h,
>  models 30h–4Fh processors have two 32-byte fetch windows, from which three micro-ops can be
>  selected.


Repository:
  rL LLVM

https://reviews.llvm.org/D53055