[PATCH] D44548: [DAGCombiner] Expand combining of FP logical operations to sign-setting FP operations
Sanjay Patel via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 9 14:33:44 PDT 2018
spatel accepted this revision.
spatel added a comment.
This revision is now accepted and ready to land.
LGTM
Nit: it would be nicer to check in the PPC tests with baseline asm as a preliminary step. That way, we'd just see the asm diff there too.
AArch64 and x86 don't have vector diffs, but for different reasons.
AArch:
bool hasBitPreservingFPLogic(EVT VT) const override {
// FIXME: Is this always true? It should be true for vectors at least.
return VT == MVT::f32 || VT == MVT::f64;
}
x86:
We're already producing the optimal 'or' instruction, and either that transform has already occurred, or this transform fires and gets folded to the same thing (I didn't step through the debug).
Repository:
rL LLVM
https://reviews.llvm.org/D44548
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