[PATCH] D52846: [AMDGPU] Add FixupVectorISel pass, currently Supports SREGs in GLOBAL LD/ST

[Ron Lieberman via Phabricator via llvm-commits]

ronlieb added inline comments.


================
Comment at: lib/Target/AMDGPU/SIFixupVectorISel.cpp:167-172
+    if (HasVdst)
+      NewGlob = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcd),
+                        MI.getOperand(0).getReg());
+    else
+      // No vdst field.
+      NewGlob = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcd));
----------------
arsenm wrote:
> Braces for both half
I thought the coding standard was no braces for single statement 'if' and 'else' , is it not ? 
I personally like braces, however staying with convention seems best.
I could also refactor it a little bit and avoid the whole topic...

    NewGlob = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcd));
    if (HasVdst)
      NewGlob->addOperand(MF, MI.getOperand(0));



https://reviews.llvm.org/D52846