[llvm] r343966 - [GlobalIsel][X86] Support G_UDIV/G_UREM/G_SREM
Alexander Ivchenko via llvm-commits
llvm-commits at lists.llvm.org
Mon Oct 8 06:40:34 PDT 2018
Author: aivchenk
Date: Mon Oct 8 06:40:34 2018
New Revision: 343966
URL: http://llvm.org/viewvc/llvm-project?rev=343966&view=rev
Log:
[GlobalIsel][X86] Support G_UDIV/G_UREM/G_SREM
Support G_UDIV/G_UREM/G_SREM. The instruction selection
code is taken from FastISel with only minor tweaks to adapt
for GlobalISel.
Differential Revision: https://reviews.llvm.org/D49781
Added:
llvm/trunk/test/CodeGen/X86/GlobalISel/x86-legalize-srem.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/x86-legalize-udiv.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/x86-legalize-urem.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/x86-select-srem.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/x86-select-udiv.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/x86-select-urem.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-legalize-srem.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-legalize-udiv.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-legalize-urem.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-select-udiv.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir
Modified:
llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp
llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp
llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-irtranslator.ll
Modified: llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp?rev=343966&r1=343965&r2=343966&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstructionSelector.cpp Mon Oct 8 06:40:34 2018
@@ -116,8 +116,8 @@ private:
bool selectImplicitDefOrPHI(MachineInstr &I, MachineRegisterInfo &MRI) const;
bool selectShift(MachineInstr &I, MachineRegisterInfo &MRI,
MachineFunction &MF) const;
- bool selectSDiv(MachineInstr &I, MachineRegisterInfo &MRI,
- MachineFunction &MF) const;
+ bool selectDivRem(MachineInstr &I, MachineRegisterInfo &MRI,
+ MachineFunction &MF) const;
bool selectIntrinsicWSideEffects(MachineInstr &I, MachineRegisterInfo &MRI,
MachineFunction &MF) const;
@@ -388,7 +388,10 @@ bool X86InstructionSelector::select(Mach
case TargetOpcode::G_LSHR:
return selectShift(I, MRI, MF);
case TargetOpcode::G_SDIV:
- return selectSDiv(I, MRI, MF);
+ case TargetOpcode::G_UDIV:
+ case TargetOpcode::G_SREM:
+ case TargetOpcode::G_UREM:
+ return selectDivRem(I, MRI, MF);
case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
return selectIntrinsicWSideEffects(I, MRI, MF);
}
@@ -1585,23 +1588,33 @@ bool X86InstructionSelector::selectShift
return true;
}
-bool X86InstructionSelector::selectSDiv(MachineInstr &I,
- MachineRegisterInfo &MRI,
- MachineFunction &MF) const {
-
- assert(I.getOpcode() == TargetOpcode::G_SDIV && "unexpected instruction");
+bool X86InstructionSelector::selectDivRem(MachineInstr &I,
+ MachineRegisterInfo &MRI,
+ MachineFunction &MF) const {
+ // The implementation of this function is taken from X86FastISel.
+ assert((I.getOpcode() == TargetOpcode::G_SDIV ||
+ I.getOpcode() == TargetOpcode::G_SREM ||
+ I.getOpcode() == TargetOpcode::G_UDIV ||
+ I.getOpcode() == TargetOpcode::G_UREM) &&
+ "unexpected instruction");
const unsigned DstReg = I.getOperand(0).getReg();
- const unsigned DividentReg = I.getOperand(1).getReg();
- const unsigned DiviserReg = I.getOperand(2).getReg();
+ const unsigned Op1Reg = I.getOperand(1).getReg();
+ const unsigned Op2Reg = I.getOperand(2).getReg();
const LLT RegTy = MRI.getType(DstReg);
- assert(RegTy == MRI.getType(DividentReg) &&
- RegTy == MRI.getType(DiviserReg) &&
+ assert(RegTy == MRI.getType(Op1Reg) && RegTy == MRI.getType(Op2Reg) &&
"Arguments and return value types must match");
const RegisterBank &RegRB = *RBI.getRegBank(DstReg, MRI, TRI);
+ if (RegRB.getID() != X86::GPRRegBankID)
+ return false;
+ const static unsigned NumTypes = 4; // i8, i16, i32, i64
+ const static unsigned NumOps = 4; // SDiv, SRem, UDiv, URem
+ const static bool S = true; // IsSigned
+ const static bool U = false; // !IsSigned
+ const static unsigned Copy = TargetOpcode::COPY;
// For the X86 IDIV instruction, in most cases the dividend
// (numerator) must be in a specific register pair highreg:lowreg,
// producing the quotient in lowreg and the remainder in highreg.
@@ -1610,57 +1623,168 @@ bool X86InstructionSelector::selectSDiv(
// exception is i8, where the dividend is defined as a single register rather
// than a register pair, and we therefore directly sign-extend the dividend
// into lowreg, instead of copying, and ignore the highreg.
- const static struct SDivEntry {
+ const static struct DivRemEntry {
+ // The following portion depends only on the data type.
unsigned SizeInBits;
- unsigned QuotientReg;
- unsigned DividentRegUpper;
- unsigned DividentRegLower;
- unsigned OpSignExtend;
- unsigned OpCopy;
- unsigned OpDiv;
- } OpTable[] = {
- {8, X86::AL, X86::NoRegister, X86::AX, 0, X86::MOVSX16rr8,
- X86::IDIV8r}, // i8
- {16, X86::AX, X86::DX, X86::AX, X86::CWD, TargetOpcode::COPY,
- X86::IDIV16r}, // i16
- {32, X86::EAX, X86::EDX, X86::EAX, X86::CDQ, TargetOpcode::COPY,
- X86::IDIV32r}, // i32
- {64, X86::RAX, X86::RDX, X86::RAX, X86::CQO, TargetOpcode::COPY,
- X86::IDIV64r} // i64
+ unsigned LowInReg; // low part of the register pair
+ unsigned HighInReg; // high part of the register pair
+ // The following portion depends on both the data type and the operation.
+ struct DivRemResult {
+ unsigned OpDivRem; // The specific DIV/IDIV opcode to use.
+ unsigned OpSignExtend; // Opcode for sign-extending lowreg into
+ // highreg, or copying a zero into highreg.
+ unsigned OpCopy; // Opcode for copying dividend into lowreg, or
+ // zero/sign-extending into lowreg for i8.
+ unsigned DivRemResultReg; // Register containing the desired result.
+ bool IsOpSigned; // Whether to use signed or unsigned form.
+ } ResultTable[NumOps];
+ } OpTable[NumTypes] = {
+ {8,
+ X86::AX,
+ 0,
+ {
+ {X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AL, S}, // SDiv
+ {X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AH, S}, // SRem
+ {X86::DIV8r, 0, X86::MOVZX16rr8, X86::AL, U}, // UDiv
+ {X86::DIV8r, 0, X86::MOVZX16rr8, X86::AH, U}, // URem
+ }}, // i8
+ {16,
+ X86::AX,
+ X86::DX,
+ {
+ {X86::IDIV16r, X86::CWD, Copy, X86::AX, S}, // SDiv
+ {X86::IDIV16r, X86::CWD, Copy, X86::DX, S}, // SRem
+ {X86::DIV16r, X86::MOV32r0, Copy, X86::AX, U}, // UDiv
+ {X86::DIV16r, X86::MOV32r0, Copy, X86::DX, U}, // URem
+ }}, // i16
+ {32,
+ X86::EAX,
+ X86::EDX,
+ {
+ {X86::IDIV32r, X86::CDQ, Copy, X86::EAX, S}, // SDiv
+ {X86::IDIV32r, X86::CDQ, Copy, X86::EDX, S}, // SRem
+ {X86::DIV32r, X86::MOV32r0, Copy, X86::EAX, U}, // UDiv
+ {X86::DIV32r, X86::MOV32r0, Copy, X86::EDX, U}, // URem
+ }}, // i32
+ {64,
+ X86::RAX,
+ X86::RDX,
+ {
+ {X86::IDIV64r, X86::CQO, Copy, X86::RAX, S}, // SDiv
+ {X86::IDIV64r, X86::CQO, Copy, X86::RDX, S}, // SRem
+ {X86::DIV64r, X86::MOV32r0, Copy, X86::RAX, U}, // UDiv
+ {X86::DIV64r, X86::MOV32r0, Copy, X86::RDX, U}, // URem
+ }}, // i64
};
- if (RegRB.getID() != X86::GPRRegBankID)
+ auto OpEntryIt = std::find_if(std::begin(OpTable), std::end(OpTable),
+ [RegTy](const DivRemEntry &El) {
+ return El.SizeInBits == RegTy.getSizeInBits();
+ });
+ if (OpEntryIt == std::end(OpTable))
return false;
- auto SDivEntryIt = std::find_if(
- std::begin(OpTable), std::end(OpTable), [RegTy](const SDivEntry &El) {
- return El.SizeInBits == RegTy.getSizeInBits();
- });
+ unsigned OpIndex;
+ switch (I.getOpcode()) {
+ default:
+ llvm_unreachable("Unexpected div/rem opcode");
+ case TargetOpcode::G_SDIV:
+ OpIndex = 0;
+ break;
+ case TargetOpcode::G_SREM:
+ OpIndex = 1;
+ break;
+ case TargetOpcode::G_UDIV:
+ OpIndex = 2;
+ break;
+ case TargetOpcode::G_UREM:
+ OpIndex = 3;
+ break;
+ }
- if (SDivEntryIt == std::end(OpTable))
- return false;
+ const DivRemEntry &TypeEntry = *OpEntryIt;
+ const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex];
const TargetRegisterClass *RegRC = getRegClass(RegTy, RegRB);
- if (!RBI.constrainGenericRegister(DividentReg, *RegRC, MRI) ||
- !RBI.constrainGenericRegister(DiviserReg, *RegRC, MRI) ||
+ if (!RBI.constrainGenericRegister(Op1Reg, *RegRC, MRI) ||
+ !RBI.constrainGenericRegister(Op2Reg, *RegRC, MRI) ||
!RBI.constrainGenericRegister(DstReg, *RegRC, MRI)) {
LLVM_DEBUG(dbgs() << "Failed to constrain " << TII.getName(I.getOpcode())
<< " operand\n");
return false;
}
- BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SDivEntryIt->OpCopy),
- SDivEntryIt->DividentRegLower)
- .addReg(DividentReg);
- if (SDivEntryIt->DividentRegUpper != X86::NoRegister)
- BuildMI(*I.getParent(), I, I.getDebugLoc(),
- TII.get(SDivEntryIt->OpSignExtend));
- BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SDivEntryIt->OpDiv))
- .addReg(DiviserReg);
- BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY),
- DstReg)
- .addReg(SDivEntryIt->QuotientReg);
+ // Move op1 into low-order input register.
+ BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpCopy),
+ TypeEntry.LowInReg)
+ .addReg(Op1Reg);
+ // Zero-extend or sign-extend into high-order input register.
+ if (OpEntry.OpSignExtend) {
+ if (OpEntry.IsOpSigned)
+ BuildMI(*I.getParent(), I, I.getDebugLoc(),
+ TII.get(OpEntry.OpSignExtend));
+ else {
+ unsigned Zero32 = MRI.createVirtualRegister(&X86::GR32RegClass);
+ BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::MOV32r0),
+ Zero32);
+
+ // Copy the zero into the appropriate sub/super/identical physical
+ // register. Unfortunately the operations needed are not uniform enough
+ // to fit neatly into the table above.
+ if (RegTy.getSizeInBits() == 16) {
+ BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy),
+ TypeEntry.HighInReg)
+ .addReg(Zero32, 0, X86::sub_16bit);
+ } else if (RegTy.getSizeInBits() == 32) {
+ BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy),
+ TypeEntry.HighInReg)
+ .addReg(Zero32);
+ } else if (RegTy.getSizeInBits() == 64) {
+ BuildMI(*I.getParent(), I, I.getDebugLoc(),
+ TII.get(TargetOpcode::SUBREG_TO_REG), TypeEntry.HighInReg)
+ .addImm(0)
+ .addReg(Zero32)
+ .addImm(X86::sub_32bit);
+ }
+ }
+ }
+ // Generate the DIV/IDIV instruction.
+ BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpDivRem))
+ .addReg(Op2Reg);
+ // For i8 remainder, we can't reference ah directly, as we'll end
+ // up with bogus copies like %r9b = COPY %ah. Reference ax
+ // instead to prevent ah references in a rex instruction.
+ //
+ // The current assumption of the fast register allocator is that isel
+ // won't generate explicit references to the GR8_NOREX registers. If
+ // the allocator and/or the backend get enhanced to be more robust in
+ // that regard, this can be, and should be, removed.
+ if ((I.getOpcode() == Instruction::SRem ||
+ I.getOpcode() == Instruction::URem) &&
+ OpEntry.DivRemResultReg == X86::AH && STI.is64Bit()) {
+ unsigned SourceSuperReg = MRI.createVirtualRegister(&X86::GR16RegClass);
+ unsigned ResultSuperReg = MRI.createVirtualRegister(&X86::GR16RegClass);
+ BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy), SourceSuperReg)
+ .addReg(X86::AX);
+
+ // Shift AX right by 8 bits instead of using AH.
+ BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SHR16ri),
+ ResultSuperReg)
+ .addReg(SourceSuperReg)
+ .addImm(8);
+ // Now reference the 8-bit subreg of the result.
+ BuildMI(*I.getParent(), I, I.getDebugLoc(),
+ TII.get(TargetOpcode::SUBREG_TO_REG))
+ .addDef(DstReg)
+ .addImm(0)
+ .addReg(ResultSuperReg)
+ .addImm(X86::sub_8bit);
+ } else {
+ BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY),
+ DstReg)
+ .addReg(OpEntry.DivRemResultReg);
+ }
I.eraseFromParent();
return true;
}
Modified: llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp?rev=343966&r1=343965&r2=343966&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86LegalizerInfo.cpp Mon Oct 8 06:40:34 2018
@@ -133,7 +133,8 @@ void X86LegalizerInfo::setLegalizerInfo3
getActionDefinitionsBuilder(G_INTTOPTR).legalFor({{p0, s32}});
// Shifts and SDIV
- getActionDefinitionsBuilder({G_SHL, G_LSHR, G_ASHR, G_SDIV})
+ getActionDefinitionsBuilder(
+ {G_SHL, G_LSHR, G_ASHR, G_SDIV, G_SREM, G_UDIV, G_UREM})
.legalFor({s8, s16, s32})
.clampScalar(0, s8, s32);
}
@@ -236,9 +237,10 @@ void X86LegalizerInfo::setLegalizerInfo6
.widenScalarToNextPow2(1);
// Shifts and SDIV
- getActionDefinitionsBuilder({G_SHL, G_LSHR, G_ASHR, G_SDIV})
- .legalFor({s8, s16, s32, s64})
- .clampScalar(0, s8, s64);
+ getActionDefinitionsBuilder(
+ {G_SHL, G_LSHR, G_ASHR, G_SDIV, G_SREM, G_UDIV, G_UREM})
+ .legalFor({s8, s16, s32, s64})
+ .clampScalar(0, s8, s64);
// Merge/Unmerge
setAction({G_MERGE_VALUES, s128}, Legal);
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/x86-legalize-srem.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/x86-legalize-srem.mir?rev=343966&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/x86-legalize-srem.mir (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/x86-legalize-srem.mir Mon Oct 8 06:40:34 2018
@@ -0,0 +1,211 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=i686-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+ ; ModuleID = 'srem.ll'
+ source_filename = "srem.ll"
+ target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
+ target triple = "i386--linux-gnu"
+
+ define i8 @test_srem_i8(i8 %arg1, i8 %arg2) {
+ %res = srem i8 %arg1, %arg2
+ ret i8 %res
+ }
+
+ define i16 @test_srem_i16(i16 %arg1, i16 %arg2) {
+ %res = srem i16 %arg1, %arg2
+ ret i16 %res
+ }
+
+ define i32 @test_srem_i32(i32 %arg1, i32 %arg2) {
+ %res = srem i32 %arg1, %arg2
+ ret i32 %res
+ }
+
+...
+---
+name: test_srem_i8
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+ - { id: 3, class: _, preferred-register: '' }
+ - { id: 4, class: _, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 4
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+ - { id: 0, type: default, offset: 4, size: 1, alignment: 4, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, type: default, offset: 0, size: 1, alignment: 16, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_srem_i8
+ ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 1 from %fixed-stack.0, align 0)
+ ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; CHECK: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 1 from %fixed-stack.1, align 0)
+ ; CHECK: [[SREM:%[0-9]+]]:_(s8) = G_SREM [[LOAD]], [[LOAD1]]
+ ; CHECK: $al = COPY [[SREM]](s8)
+ ; CHECK: RET 0, implicit $al
+ %2:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ %0:_(s8) = G_LOAD %2(p0) :: (invariant load 1 from %fixed-stack.1, align 0)
+ %3:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ %1:_(s8) = G_LOAD %3(p0) :: (invariant load 1 from %fixed-stack.0, align 0)
+ %4:_(s8) = G_SREM %0, %1
+ $al = COPY %4(s8)
+ RET 0, implicit $al
+
+...
+---
+name: test_srem_i16
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+ - { id: 3, class: _, preferred-register: '' }
+ - { id: 4, class: _, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 4
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+ - { id: 0, type: default, offset: 4, size: 2, alignment: 4, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, type: default, offset: 0, size: 2, alignment: 16, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_srem_i16
+ ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 2 from %fixed-stack.0, align 0)
+ ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; CHECK: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 2 from %fixed-stack.1, align 0)
+ ; CHECK: [[SREM:%[0-9]+]]:_(s16) = G_SREM [[LOAD]], [[LOAD1]]
+ ; CHECK: $ax = COPY [[SREM]](s16)
+ ; CHECK: RET 0, implicit $ax
+ %2:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ %0:_(s16) = G_LOAD %2(p0) :: (invariant load 2 from %fixed-stack.1, align 0)
+ %3:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ %1:_(s16) = G_LOAD %3(p0) :: (invariant load 2 from %fixed-stack.0, align 0)
+ %4:_(s16) = G_SREM %0, %1
+ $ax = COPY %4(s16)
+ RET 0, implicit $ax
+
+...
+---
+name: test_srem_i32
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+ - { id: 3, class: _, preferred-register: '' }
+ - { id: 4, class: _, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 4
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+ - { id: 0, type: default, offset: 4, size: 4, alignment: 4, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, type: default, offset: 0, size: 4, alignment: 16, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_srem_i32
+ ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+ ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 4 from %fixed-stack.1, align 0)
+ ; CHECK: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[LOAD]], [[LOAD1]]
+ ; CHECK: $eax = COPY [[SREM]](s32)
+ ; CHECK: RET 0, implicit $eax
+ %2:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ %0:_(s32) = G_LOAD %2(p0) :: (invariant load 4 from %fixed-stack.1, align 0)
+ %3:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ %1:_(s32) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+ %4:_(s32) = G_SREM %0, %1
+ $eax = COPY %4(s32)
+ RET 0, implicit $eax
+
+...
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/x86-legalize-udiv.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/x86-legalize-udiv.mir?rev=343966&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/x86-legalize-udiv.mir (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/x86-legalize-udiv.mir Mon Oct 8 06:40:34 2018
@@ -0,0 +1,195 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=i686-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+ ; ModuleID = 'udiv.ll'
+ source_filename = "udiv.ll"
+ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+ define i8 @test_udiv_i8(i8 %arg1, i8 %arg2) {
+ %res = udiv i8 %arg1, %arg2
+ ret i8 %res
+ }
+
+ define i16 @test_udiv_i16(i16 %arg1, i16 %arg2) {
+ %res = udiv i16 %arg1, %arg2
+ ret i16 %res
+ }
+
+ define i32 @test_udiv_i32(i32 %arg1, i32 %arg2) {
+ %res = udiv i32 %arg1, %arg2
+ ret i32 %res
+ }
+
+...
+---
+name: test_udiv_i8
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+ - { id: 3, class: _, preferred-register: '' }
+ - { id: 4, class: _, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $edi, $esi
+
+ ; CHECK-LABEL: name: test_udiv_i8
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
+ ; CHECK: [[UDIV:%[0-9]+]]:_(s8) = G_UDIV [[TRUNC]], [[TRUNC1]]
+ ; CHECK: $al = COPY [[UDIV]](s8)
+ ; CHECK: RET 0, implicit $al
+ %2:_(s32) = COPY $edi
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:_(s32) = COPY $esi
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_UDIV %0, %1
+ $al = COPY %4(s8)
+ RET 0, implicit $al
+
+...
+---
+name: test_udiv_i16
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+ - { id: 3, class: _, preferred-register: '' }
+ - { id: 4, class: _, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $edi, $esi
+
+ ; CHECK-LABEL: name: test_udiv_i16
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK: [[UDIV:%[0-9]+]]:_(s16) = G_UDIV [[TRUNC]], [[TRUNC1]]
+ ; CHECK: $ax = COPY [[UDIV]](s16)
+ ; CHECK: RET 0, implicit $ax
+ %2:_(s32) = COPY $edi
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:_(s32) = COPY $esi
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_UDIV %0, %1
+ $ax = COPY %4(s16)
+ RET 0, implicit $ax
+
+...
+---
+name: test_udiv_i32
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $edi, $esi
+
+ ; CHECK-LABEL: name: test_udiv_i32
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
+ ; CHECK: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[COPY]], [[COPY1]]
+ ; CHECK: $eax = COPY [[UDIV]](s32)
+ ; CHECK: RET 0, implicit $eax
+ %0:_(s32) = COPY $edi
+ %1:_(s32) = COPY $esi
+ %2:_(s32) = G_UDIV %0, %1
+ $eax = COPY %2(s32)
+ RET 0, implicit $eax
+
+...
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/x86-legalize-urem.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/x86-legalize-urem.mir?rev=343966&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/x86-legalize-urem.mir (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/x86-legalize-urem.mir Mon Oct 8 06:40:34 2018
@@ -0,0 +1,211 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=i686-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+ ; ModuleID = 'urem.ll'
+ source_filename = "urem.ll"
+ target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
+ target triple = "i386--linux-gnu"
+
+ define i8 @test_urem_i8(i8 %arg1, i8 %arg2) {
+ %res = urem i8 %arg1, %arg2
+ ret i8 %res
+ }
+
+ define i16 @test_urem_i16(i16 %arg1, i16 %arg2) {
+ %res = urem i16 %arg1, %arg2
+ ret i16 %res
+ }
+
+ define i32 @test_urem_i32(i32 %arg1, i32 %arg2) {
+ %res = urem i32 %arg1, %arg2
+ ret i32 %res
+ }
+
+...
+---
+name: test_urem_i8
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+ - { id: 3, class: _, preferred-register: '' }
+ - { id: 4, class: _, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 4
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+ - { id: 0, type: default, offset: 4, size: 1, alignment: 4, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, type: default, offset: 0, size: 1, alignment: 16, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_urem_i8
+ ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 1 from %fixed-stack.0, align 0)
+ ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; CHECK: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 1 from %fixed-stack.1, align 0)
+ ; CHECK: [[UREM:%[0-9]+]]:_(s8) = G_UREM [[LOAD]], [[LOAD1]]
+ ; CHECK: $al = COPY [[UREM]](s8)
+ ; CHECK: RET 0, implicit $al
+ %2:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ %0:_(s8) = G_LOAD %2(p0) :: (invariant load 1 from %fixed-stack.1, align 0)
+ %3:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ %1:_(s8) = G_LOAD %3(p0) :: (invariant load 1 from %fixed-stack.0, align 0)
+ %4:_(s8) = G_UREM %0, %1
+ $al = COPY %4(s8)
+ RET 0, implicit $al
+
+...
+---
+name: test_urem_i16
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+ - { id: 3, class: _, preferred-register: '' }
+ - { id: 4, class: _, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 4
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+ - { id: 0, type: default, offset: 4, size: 2, alignment: 4, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, type: default, offset: 0, size: 2, alignment: 16, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_urem_i16
+ ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 2 from %fixed-stack.0, align 0)
+ ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; CHECK: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 2 from %fixed-stack.1, align 0)
+ ; CHECK: [[UREM:%[0-9]+]]:_(s16) = G_UREM [[LOAD]], [[LOAD1]]
+ ; CHECK: $ax = COPY [[UREM]](s16)
+ ; CHECK: RET 0, implicit $ax
+ %2:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ %0:_(s16) = G_LOAD %2(p0) :: (invariant load 2 from %fixed-stack.1, align 0)
+ %3:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ %1:_(s16) = G_LOAD %3(p0) :: (invariant load 2 from %fixed-stack.0, align 0)
+ %4:_(s16) = G_UREM %0, %1
+ $ax = COPY %4(s16)
+ RET 0, implicit $ax
+
+...
+---
+name: test_urem_i32
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+ - { id: 3, class: _, preferred-register: '' }
+ - { id: 4, class: _, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 4
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+ - { id: 0, type: default, offset: 4, size: 4, alignment: 4, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, type: default, offset: 0, size: 4, alignment: 16, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_urem_i32
+ ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+ ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ ; CHECK: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load 4 from %fixed-stack.1, align 0)
+ ; CHECK: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[LOAD]], [[LOAD1]]
+ ; CHECK: $eax = COPY [[UREM]](s32)
+ ; CHECK: RET 0, implicit $eax
+ %2:_(p0) = G_FRAME_INDEX %fixed-stack.1
+ %0:_(s32) = G_LOAD %2(p0) :: (invariant load 4 from %fixed-stack.1, align 0)
+ %3:_(p0) = G_FRAME_INDEX %fixed-stack.0
+ %1:_(s32) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+ %4:_(s32) = G_UREM %0, %1
+ $eax = COPY %4(s32)
+ RET 0, implicit $eax
+
+...
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/x86-select-srem.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/x86-select-srem.mir?rev=343966&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/x86-select-srem.mir (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/x86-select-srem.mir Mon Oct 8 06:40:34 2018
@@ -0,0 +1,213 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=i386-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+ ; ModuleID = 'srem.ll'
+ source_filename = "srem.ll"
+ target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
+ target triple = "i386--linux-gnu"
+
+ define i8 @test_srem_i8(i8 %arg1, i8 %arg2) {
+ %res = srem i8 %arg1, %arg2
+ ret i8 %res
+ }
+
+ define i16 @test_srem_i16(i16 %arg1, i16 %arg2) {
+ %res = srem i16 %arg1, %arg2
+ ret i16 %res
+ }
+
+ define i32 @test_srem_i32(i32 %arg1, i32 %arg2) {
+ %res = srem i32 %arg1, %arg2
+ ret i32 %res
+ }
+
+...
+---
+name: test_srem_i8
+alignment: 4
+exposesReturnsTwice: false
+legalized: true
+regBankSelected: true
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr, preferred-register: '' }
+ - { id: 1, class: gpr, preferred-register: '' }
+ - { id: 2, class: gpr, preferred-register: '' }
+ - { id: 3, class: gpr, preferred-register: '' }
+ - { id: 4, class: gpr, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 4
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+ - { id: 0, type: default, offset: 4, size: 1, alignment: 4, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, type: default, offset: 0, size: 1, alignment: 16, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_srem_i8
+ ; CHECK: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (invariant load 1 from %fixed-stack.0, align 0)
+ ; CHECK: [[MOV8rm1:%[0-9]+]]:gr8 = MOV8rm %fixed-stack.1, 1, $noreg, 0, $noreg :: (invariant load 1 from %fixed-stack.1, align 0)
+ ; CHECK: $ax = MOVSX16rr8 [[MOV8rm]]
+ ; CHECK: IDIV8r [[MOV8rm1]], implicit-def $al, implicit-def $ah, implicit-def $eflags, implicit $ax
+ ; CHECK: [[COPY:%[0-9]+]]:gr8 = COPY $ah
+ ; CHECK: $al = COPY [[COPY]]
+ ; CHECK: RET 0, implicit $al
+ %2:gpr(p0) = G_FRAME_INDEX %fixed-stack.1
+ %0:gpr(s8) = G_LOAD %2(p0) :: (invariant load 1 from %fixed-stack.1, align 0)
+ %3:gpr(p0) = G_FRAME_INDEX %fixed-stack.0
+ %1:gpr(s8) = G_LOAD %3(p0) :: (invariant load 1 from %fixed-stack.0, align 0)
+ %4:gpr(s8) = G_SREM %0, %1
+ $al = COPY %4(s8)
+ RET 0, implicit $al
+
+...
+---
+name: test_srem_i16
+alignment: 4
+exposesReturnsTwice: false
+legalized: true
+regBankSelected: true
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr, preferred-register: '' }
+ - { id: 1, class: gpr, preferred-register: '' }
+ - { id: 2, class: gpr, preferred-register: '' }
+ - { id: 3, class: gpr, preferred-register: '' }
+ - { id: 4, class: gpr, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 4
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+ - { id: 0, type: default, offset: 4, size: 2, alignment: 4, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, type: default, offset: 0, size: 2, alignment: 16, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_srem_i16
+ ; CHECK: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (invariant load 2 from %fixed-stack.0, align 0)
+ ; CHECK: [[MOV16rm1:%[0-9]+]]:gr16 = MOV16rm %fixed-stack.1, 1, $noreg, 0, $noreg :: (invariant load 2 from %fixed-stack.1, align 0)
+ ; CHECK: $ax = COPY [[MOV16rm]]
+ ; CHECK: CWD implicit-def $ax, implicit-def $dx, implicit $ax
+ ; CHECK: IDIV16r [[MOV16rm1]], implicit-def $ax, implicit-def $dx, implicit-def $eflags, implicit $ax, implicit $dx
+ ; CHECK: [[COPY:%[0-9]+]]:gr16 = COPY $dx
+ ; CHECK: $ax = COPY [[COPY]]
+ ; CHECK: RET 0, implicit $ax
+ %2:gpr(p0) = G_FRAME_INDEX %fixed-stack.1
+ %0:gpr(s16) = G_LOAD %2(p0) :: (invariant load 2 from %fixed-stack.1, align 0)
+ %3:gpr(p0) = G_FRAME_INDEX %fixed-stack.0
+ %1:gpr(s16) = G_LOAD %3(p0) :: (invariant load 2 from %fixed-stack.0, align 0)
+ %4:gpr(s16) = G_SREM %0, %1
+ $ax = COPY %4(s16)
+ RET 0, implicit $ax
+
+...
+---
+name: test_srem_i32
+alignment: 4
+exposesReturnsTwice: false
+legalized: true
+regBankSelected: true
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr, preferred-register: '' }
+ - { id: 1, class: gpr, preferred-register: '' }
+ - { id: 2, class: gpr, preferred-register: '' }
+ - { id: 3, class: gpr, preferred-register: '' }
+ - { id: 4, class: gpr, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 4
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+ - { id: 0, type: default, offset: 4, size: 4, alignment: 4, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, type: default, offset: 0, size: 4, alignment: 16, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_srem_i32
+ ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (invariant load 4 from %fixed-stack.0, align 0)
+ ; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.1, 1, $noreg, 0, $noreg :: (invariant load 4 from %fixed-stack.1, align 0)
+ ; CHECK: $eax = COPY [[MOV32rm]]
+ ; CHECK: CDQ implicit-def $eax, implicit-def $edx, implicit $eax
+ ; CHECK: IDIV32r [[MOV32rm1]], implicit-def $eax, implicit-def $edx, implicit-def $eflags, implicit $eax, implicit $edx
+ ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edx
+ ; CHECK: $eax = COPY [[COPY]]
+ ; CHECK: RET 0, implicit $eax
+ %2:gpr(p0) = G_FRAME_INDEX %fixed-stack.1
+ %0:gpr(s32) = G_LOAD %2(p0) :: (invariant load 4 from %fixed-stack.1, align 0)
+ %3:gpr(p0) = G_FRAME_INDEX %fixed-stack.0
+ %1:gpr(s32) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+ %4:gpr(s32) = G_SREM %0, %1
+ $eax = COPY %4(s32)
+ RET 0, implicit $eax
+
+...
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/x86-select-udiv.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/x86-select-udiv.mir?rev=343966&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/x86-select-udiv.mir (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/x86-select-udiv.mir Mon Oct 8 06:40:34 2018
@@ -0,0 +1,215 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=i386-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+ ; ModuleID = 'udiv.ll'
+ source_filename = "udiv.ll"
+ target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
+ target triple = "i386--linux-gnu"
+
+ define i8 @test_udiv_i8(i8 %arg1, i8 %arg2) {
+ %res = udiv i8 %arg1, %arg2
+ ret i8 %res
+ }
+
+ define i16 @test_udiv_i16(i16 %arg1, i16 %arg2) {
+ %res = udiv i16 %arg1, %arg2
+ ret i16 %res
+ }
+
+ define i32 @test_udiv_i32(i32 %arg1, i32 %arg2) {
+ %res = udiv i32 %arg1, %arg2
+ ret i32 %res
+ }
+
+...
+---
+name: test_udiv_i8
+alignment: 4
+exposesReturnsTwice: false
+legalized: true
+regBankSelected: true
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr, preferred-register: '' }
+ - { id: 1, class: gpr, preferred-register: '' }
+ - { id: 2, class: gpr, preferred-register: '' }
+ - { id: 3, class: gpr, preferred-register: '' }
+ - { id: 4, class: gpr, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 4
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+ - { id: 0, type: default, offset: 4, size: 1, alignment: 4, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, type: default, offset: 0, size: 1, alignment: 16, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_udiv_i8
+ ; CHECK: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (invariant load 1 from %fixed-stack.0, align 0)
+ ; CHECK: [[MOV8rm1:%[0-9]+]]:gr8 = MOV8rm %fixed-stack.1, 1, $noreg, 0, $noreg :: (invariant load 1 from %fixed-stack.1, align 0)
+ ; CHECK: $ax = MOVZX16rr8 [[MOV8rm]]
+ ; CHECK: DIV8r [[MOV8rm1]], implicit-def $al, implicit-def $ah, implicit-def $eflags, implicit $ax
+ ; CHECK: [[COPY:%[0-9]+]]:gr8 = COPY $al
+ ; CHECK: $al = COPY [[COPY]]
+ ; CHECK: RET 0, implicit $al
+ %2:gpr(p0) = G_FRAME_INDEX %fixed-stack.1
+ %0:gpr(s8) = G_LOAD %2(p0) :: (invariant load 1 from %fixed-stack.1, align 0)
+ %3:gpr(p0) = G_FRAME_INDEX %fixed-stack.0
+ %1:gpr(s8) = G_LOAD %3(p0) :: (invariant load 1 from %fixed-stack.0, align 0)
+ %4:gpr(s8) = G_UDIV %0, %1
+ $al = COPY %4(s8)
+ RET 0, implicit $al
+
+...
+---
+name: test_udiv_i16
+alignment: 4
+exposesReturnsTwice: false
+legalized: true
+regBankSelected: true
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr, preferred-register: '' }
+ - { id: 1, class: gpr, preferred-register: '' }
+ - { id: 2, class: gpr, preferred-register: '' }
+ - { id: 3, class: gpr, preferred-register: '' }
+ - { id: 4, class: gpr, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 4
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+ - { id: 0, type: default, offset: 4, size: 2, alignment: 4, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, type: default, offset: 0, size: 2, alignment: 16, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_udiv_i16
+ ; CHECK: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (invariant load 2 from %fixed-stack.0, align 0)
+ ; CHECK: [[MOV16rm1:%[0-9]+]]:gr16 = MOV16rm %fixed-stack.1, 1, $noreg, 0, $noreg :: (invariant load 2 from %fixed-stack.1, align 0)
+ ; CHECK: $ax = COPY [[MOV16rm]]
+ ; CHECK: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+ ; CHECK: $dx = COPY [[MOV32r0_]].sub_16bit
+ ; CHECK: DIV16r [[MOV16rm1]], implicit-def $ax, implicit-def $dx, implicit-def $eflags, implicit $ax, implicit $dx
+ ; CHECK: [[COPY:%[0-9]+]]:gr16 = COPY $ax
+ ; CHECK: $ax = COPY [[COPY]]
+ ; CHECK: RET 0, implicit $ax
+ %2:gpr(p0) = G_FRAME_INDEX %fixed-stack.1
+ %0:gpr(s16) = G_LOAD %2(p0) :: (invariant load 2 from %fixed-stack.1, align 0)
+ %3:gpr(p0) = G_FRAME_INDEX %fixed-stack.0
+ %1:gpr(s16) = G_LOAD %3(p0) :: (invariant load 2 from %fixed-stack.0, align 0)
+ %4:gpr(s16) = G_UDIV %0, %1
+ $ax = COPY %4(s16)
+ RET 0, implicit $ax
+
+...
+---
+name: test_udiv_i32
+alignment: 4
+exposesReturnsTwice: false
+legalized: true
+regBankSelected: true
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr, preferred-register: '' }
+ - { id: 1, class: gpr, preferred-register: '' }
+ - { id: 2, class: gpr, preferred-register: '' }
+ - { id: 3, class: gpr, preferred-register: '' }
+ - { id: 4, class: gpr, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 4
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+ - { id: 0, type: default, offset: 4, size: 4, alignment: 4, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, type: default, offset: 0, size: 4, alignment: 16, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_udiv_i32
+ ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (invariant load 4 from %fixed-stack.0, align 0)
+ ; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.1, 1, $noreg, 0, $noreg :: (invariant load 4 from %fixed-stack.1, align 0)
+ ; CHECK: $eax = COPY [[MOV32rm]]
+ ; CHECK: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+ ; CHECK: $edx = COPY [[MOV32r0_]]
+ ; CHECK: DIV32r [[MOV32rm1]], implicit-def $eax, implicit-def $edx, implicit-def $eflags, implicit $eax, implicit $edx
+ ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $eax
+ ; CHECK: $eax = COPY [[COPY]]
+ ; CHECK: RET 0, implicit $eax
+ %2:gpr(p0) = G_FRAME_INDEX %fixed-stack.1
+ %0:gpr(s32) = G_LOAD %2(p0) :: (invariant load 4 from %fixed-stack.1, align 0)
+ %3:gpr(p0) = G_FRAME_INDEX %fixed-stack.0
+ %1:gpr(s32) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+ %4:gpr(s32) = G_UDIV %0, %1
+ $eax = COPY %4(s32)
+ RET 0, implicit $eax
+
+...
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/x86-select-urem.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/x86-select-urem.mir?rev=343966&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/x86-select-urem.mir (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/x86-select-urem.mir Mon Oct 8 06:40:34 2018
@@ -0,0 +1,215 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=i386-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+ ; ModuleID = 'urem.ll'
+ source_filename = "urem.ll"
+ target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
+ target triple = "i386--linux-gnu"
+
+ define i8 @test_urem_i8(i8 %arg1, i8 %arg2) {
+ %res = urem i8 %arg1, %arg2
+ ret i8 %res
+ }
+
+ define i16 @test_urem_i16(i16 %arg1, i16 %arg2) {
+ %res = urem i16 %arg1, %arg2
+ ret i16 %res
+ }
+
+ define i32 @test_urem_i32(i32 %arg1, i32 %arg2) {
+ %res = urem i32 %arg1, %arg2
+ ret i32 %res
+ }
+
+...
+---
+name: test_urem_i8
+alignment: 4
+exposesReturnsTwice: false
+legalized: true
+regBankSelected: true
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr, preferred-register: '' }
+ - { id: 1, class: gpr, preferred-register: '' }
+ - { id: 2, class: gpr, preferred-register: '' }
+ - { id: 3, class: gpr, preferred-register: '' }
+ - { id: 4, class: gpr, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 4
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+ - { id: 0, type: default, offset: 4, size: 1, alignment: 4, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, type: default, offset: 0, size: 1, alignment: 16, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_urem_i8
+ ; CHECK: [[MOV8rm:%[0-9]+]]:gr8 = MOV8rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (invariant load 1 from %fixed-stack.0, align 0)
+ ; CHECK: [[MOV8rm1:%[0-9]+]]:gr8 = MOV8rm %fixed-stack.1, 1, $noreg, 0, $noreg :: (invariant load 1 from %fixed-stack.1, align 0)
+ ; CHECK: $ax = MOVZX16rr8 [[MOV8rm]]
+ ; CHECK: DIV8r [[MOV8rm1]], implicit-def $al, implicit-def $ah, implicit-def $eflags, implicit $ax
+ ; CHECK: [[COPY:%[0-9]+]]:gr8 = COPY $ah
+ ; CHECK: $al = COPY [[COPY]]
+ ; CHECK: RET 0, implicit $al
+ %2:gpr(p0) = G_FRAME_INDEX %fixed-stack.1
+ %0:gpr(s8) = G_LOAD %2(p0) :: (invariant load 1 from %fixed-stack.1, align 0)
+ %3:gpr(p0) = G_FRAME_INDEX %fixed-stack.0
+ %1:gpr(s8) = G_LOAD %3(p0) :: (invariant load 1 from %fixed-stack.0, align 0)
+ %4:gpr(s8) = G_UREM %0, %1
+ $al = COPY %4(s8)
+ RET 0, implicit $al
+
+...
+---
+name: test_urem_i16
+alignment: 4
+exposesReturnsTwice: false
+legalized: true
+regBankSelected: true
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr, preferred-register: '' }
+ - { id: 1, class: gpr, preferred-register: '' }
+ - { id: 2, class: gpr, preferred-register: '' }
+ - { id: 3, class: gpr, preferred-register: '' }
+ - { id: 4, class: gpr, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 4
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+ - { id: 0, type: default, offset: 4, size: 2, alignment: 4, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, type: default, offset: 0, size: 2, alignment: 16, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_urem_i16
+ ; CHECK: [[MOV16rm:%[0-9]+]]:gr16 = MOV16rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (invariant load 2 from %fixed-stack.0, align 0)
+ ; CHECK: [[MOV16rm1:%[0-9]+]]:gr16 = MOV16rm %fixed-stack.1, 1, $noreg, 0, $noreg :: (invariant load 2 from %fixed-stack.1, align 0)
+ ; CHECK: $ax = COPY [[MOV16rm]]
+ ; CHECK: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+ ; CHECK: $dx = COPY [[MOV32r0_]].sub_16bit
+ ; CHECK: DIV16r [[MOV16rm1]], implicit-def $ax, implicit-def $dx, implicit-def $eflags, implicit $ax, implicit $dx
+ ; CHECK: [[COPY:%[0-9]+]]:gr16 = COPY $dx
+ ; CHECK: $ax = COPY [[COPY]]
+ ; CHECK: RET 0, implicit $ax
+ %2:gpr(p0) = G_FRAME_INDEX %fixed-stack.1
+ %0:gpr(s16) = G_LOAD %2(p0) :: (invariant load 2 from %fixed-stack.1, align 0)
+ %3:gpr(p0) = G_FRAME_INDEX %fixed-stack.0
+ %1:gpr(s16) = G_LOAD %3(p0) :: (invariant load 2 from %fixed-stack.0, align 0)
+ %4:gpr(s16) = G_UREM %0, %1
+ $ax = COPY %4(s16)
+ RET 0, implicit $ax
+
+...
+---
+name: test_urem_i32
+alignment: 4
+exposesReturnsTwice: false
+legalized: true
+regBankSelected: true
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr, preferred-register: '' }
+ - { id: 1, class: gpr, preferred-register: '' }
+ - { id: 2, class: gpr, preferred-register: '' }
+ - { id: 3, class: gpr, preferred-register: '' }
+ - { id: 4, class: gpr, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 4
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+ - { id: 0, type: default, offset: 4, size: 4, alignment: 4, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+ - { id: 1, type: default, offset: 0, size: 4, alignment: 16, stack-id: 0,
+ isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true,
+ debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ ; CHECK-LABEL: name: test_urem_i32
+ ; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.0, 1, $noreg, 0, $noreg :: (invariant load 4 from %fixed-stack.0, align 0)
+ ; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %fixed-stack.1, 1, $noreg, 0, $noreg :: (invariant load 4 from %fixed-stack.1, align 0)
+ ; CHECK: $eax = COPY [[MOV32rm]]
+ ; CHECK: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+ ; CHECK: $edx = COPY [[MOV32r0_]]
+ ; CHECK: DIV32r [[MOV32rm1]], implicit-def $eax, implicit-def $edx, implicit-def $eflags, implicit $eax, implicit $edx
+ ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edx
+ ; CHECK: $eax = COPY [[COPY]]
+ ; CHECK: RET 0, implicit $eax
+ %2:gpr(p0) = G_FRAME_INDEX %fixed-stack.1
+ %0:gpr(s32) = G_LOAD %2(p0) :: (invariant load 4 from %fixed-stack.1, align 0)
+ %3:gpr(p0) = G_FRAME_INDEX %fixed-stack.0
+ %1:gpr(s32) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
+ %4:gpr(s32) = G_UREM %0, %1
+ $eax = COPY %4(s32)
+ RET 0, implicit $eax
+
+...
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-irtranslator.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-irtranslator.ll?rev=343966&r1=343965&r2=343966&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-irtranslator.ll (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-irtranslator.ll Mon Oct 8 06:40:34 2018
@@ -198,3 +198,171 @@ define float @test_fptrunc(double %in) {
%res = fptrunc double %in to float
ret float %res
}
+
+define i8 @test_srem_i8(i8 %arg1, i8 %arg2) {
+ ; CHECK-LABEL: name: test_srem_i8
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
+ ; CHECK: [[SREM:%[0-9]+]]:_(s8) = G_SREM [[TRUNC]], [[TRUNC1]]
+ ; CHECK: $al = COPY [[SREM]](s8)
+ ; CHECK: RET 0, implicit $al
+ %res = srem i8 %arg1, %arg2
+ ret i8 %res
+}
+
+define i16 @test_srem_i16(i16 %arg1, i16 %arg2) {
+ ; CHECK-LABEL: name: test_srem_i16
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK: [[SREM:%[0-9]+]]:_(s16) = G_SREM [[TRUNC]], [[TRUNC1]]
+ ; CHECK: $ax = COPY [[SREM]](s16)
+ ; CHECK: RET 0, implicit $ax
+ %res = srem i16 %arg1, %arg2
+ ret i16 %res
+}
+
+define i32 @test_srem_i32(i32 %arg1, i32 %arg2) {
+ ; CHECK-LABEL: name: test_srem_i32
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
+ ; CHECK: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[COPY]], [[COPY1]]
+ ; CHECK: $eax = COPY [[SREM]](s32)
+ ; CHECK: RET 0, implicit $eax
+ %res = srem i32 %arg1, %arg2
+ ret i32 %res
+}
+
+define i64 @test_srem_i64(i64 %arg1, i64 %arg2) {
+ ; CHECK-LABEL: name: test_srem_i64
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: liveins: $rdi, $rsi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi
+ ; CHECK: [[SREM:%[0-9]+]]:_(s64) = G_SREM [[COPY]], [[COPY1]]
+ ; CHECK: $rax = COPY [[SREM]](s64)
+ ; CHECK: RET 0, implicit $rax
+ %res = srem i64 %arg1, %arg2
+ ret i64 %res
+}
+
+define i8 @test_udiv_i8(i8 %arg1, i8 %arg2) {
+ ; CHECK-LABEL: name: test_udiv_i8
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
+ ; CHECK: [[UDIV:%[0-9]+]]:_(s8) = G_UDIV [[TRUNC]], [[TRUNC1]]
+ ; CHECK: $al = COPY [[UDIV]](s8)
+ ; CHECK: RET 0, implicit $al
+ %res = udiv i8 %arg1, %arg2
+ ret i8 %res
+}
+
+define i16 @test_udiv_i16(i16 %arg1, i16 %arg2) {
+ ; CHECK-LABEL: name: test_udiv_i16
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK: [[UDIV:%[0-9]+]]:_(s16) = G_UDIV [[TRUNC]], [[TRUNC1]]
+ ; CHECK: $ax = COPY [[UDIV]](s16)
+ ; CHECK: RET 0, implicit $ax
+ %res = udiv i16 %arg1, %arg2
+ ret i16 %res
+}
+
+define i32 @test_udiv_i32(i32 %arg1, i32 %arg2) {
+ ; CHECK-LABEL: name: test_udiv_i32
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
+ ; CHECK: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[COPY]], [[COPY1]]
+ ; CHECK: $eax = COPY [[UDIV]](s32)
+ ; CHECK: RET 0, implicit $eax
+ %res = udiv i32 %arg1, %arg2
+ ret i32 %res
+}
+
+define i64 @test_udiv_i64(i64 %arg1, i64 %arg2) {
+ ; CHECK-LABEL: name: test_udiv_i64
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: liveins: $rdi, $rsi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi
+ ; CHECK: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[COPY]], [[COPY1]]
+ ; CHECK: $rax = COPY [[UDIV]](s64)
+ ; CHECK: RET 0, implicit $rax
+ %res = udiv i64 %arg1, %arg2
+ ret i64 %res
+}
+
+define i8 @test_urem_i8(i8 %arg1, i8 %arg2) {
+ ; CHECK-LABEL: name: test_urem_i8
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
+ ; CHECK: [[UREM:%[0-9]+]]:_(s8) = G_UREM [[TRUNC]], [[TRUNC1]]
+ ; CHECK: $al = COPY [[UREM]](s8)
+ ; CHECK: RET 0, implicit $al
+ %res = urem i8 %arg1, %arg2
+ ret i8 %res
+}
+
+define i16 @test_urem_i16(i16 %arg1, i16 %arg2) {
+ ; CHECK-LABEL: name: test_urem_i16
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK: [[UREM:%[0-9]+]]:_(s16) = G_UREM [[TRUNC]], [[TRUNC1]]
+ ; CHECK: $ax = COPY [[UREM]](s16)
+ ; CHECK: RET 0, implicit $ax
+ %res = urem i16 %arg1, %arg2
+ ret i16 %res
+}
+
+define i32 @test_urem_i32(i32 %arg1, i32 %arg2) {
+ ; CHECK-LABEL: name: test_urem_i32
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
+ ; CHECK: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[COPY]], [[COPY1]]
+ ; CHECK: $eax = COPY [[UREM]](s32)
+ ; CHECK: RET 0, implicit $eax
+ %res = urem i32 %arg1, %arg2
+ ret i32 %res
+}
+
+define i64 @test_urem_i64(i64 %arg1, i64 %arg2) {
+ ; CHECK-LABEL: name: test_urem_i64
+ ; CHECK: bb.1 (%ir-block.0):
+ ; CHECK: liveins: $rdi, $rsi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi
+ ; CHECK: [[UREM:%[0-9]+]]:_(s64) = G_UREM [[COPY]], [[COPY1]]
+ ; CHECK: $rax = COPY [[UREM]](s64)
+ ; CHECK: RET 0, implicit $rax
+ %res = urem i64 %arg1, %arg2
+ ret i64 %res
+}
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-legalize-srem.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-legalize-srem.mir?rev=343966&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-legalize-srem.mir (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-legalize-srem.mir Mon Oct 8 06:40:34 2018
@@ -0,0 +1,253 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+ ; ModuleID = 'srem.ll'
+ source_filename = "srem.ll"
+ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+ define i8 @test_srem_i8(i8 %arg1, i8 %arg2) {
+ %res = srem i8 %arg1, %arg2
+ ret i8 %res
+ }
+
+ define i16 @test_srem_i16(i16 %arg1, i16 %arg2) {
+ %res = srem i16 %arg1, %arg2
+ ret i16 %res
+ }
+
+ define i32 @test_srem_i32(i32 %arg1, i32 %arg2) {
+ %res = srem i32 %arg1, %arg2
+ ret i32 %res
+ }
+
+ define i64 @test_srem_i64(i64 %arg1, i64 %arg2) {
+ %res = srem i64 %arg1, %arg2
+ ret i64 %res
+ }
+
+...
+---
+name: test_srem_i8
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+ - { id: 3, class: _, preferred-register: '' }
+ - { id: 4, class: _, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $edi, $esi
+
+ ; CHECK-LABEL: name: test_srem_i8
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
+ ; CHECK: [[SREM:%[0-9]+]]:_(s8) = G_SREM [[TRUNC]], [[TRUNC1]]
+ ; CHECK: $al = COPY [[SREM]](s8)
+ ; CHECK: RET 0, implicit $al
+ %2:_(s32) = COPY $edi
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:_(s32) = COPY $esi
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_SREM %0, %1
+ $al = COPY %4(s8)
+ RET 0, implicit $al
+
+...
+---
+name: test_srem_i16
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+ - { id: 3, class: _, preferred-register: '' }
+ - { id: 4, class: _, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $edi, $esi
+
+ ; CHECK-LABEL: name: test_srem_i16
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK: [[SREM:%[0-9]+]]:_(s16) = G_SREM [[TRUNC]], [[TRUNC1]]
+ ; CHECK: $ax = COPY [[SREM]](s16)
+ ; CHECK: RET 0, implicit $ax
+ %2:_(s32) = COPY $edi
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:_(s32) = COPY $esi
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_SREM %0, %1
+ $ax = COPY %4(s16)
+ RET 0, implicit $ax
+
+...
+---
+name: test_srem_i32
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $edi, $esi
+
+ ; CHECK-LABEL: name: test_srem_i32
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
+ ; CHECK: [[SREM:%[0-9]+]]:_(s32) = G_SREM [[COPY]], [[COPY1]]
+ ; CHECK: $eax = COPY [[SREM]](s32)
+ ; CHECK: RET 0, implicit $eax
+ %0:_(s32) = COPY $edi
+ %1:_(s32) = COPY $esi
+ %2:_(s32) = G_SREM %0, %1
+ $eax = COPY %2(s32)
+ RET 0, implicit $eax
+
+...
+---
+name: test_srem_i64
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $rdi, $rsi
+
+ ; CHECK-LABEL: name: test_srem_i64
+ ; CHECK: liveins: $rdi, $rsi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi
+ ; CHECK: [[SREM:%[0-9]+]]:_(s64) = G_SREM [[COPY]], [[COPY1]]
+ ; CHECK: $rax = COPY [[SREM]](s64)
+ ; CHECK: RET 0, implicit $rax
+ %0:_(s64) = COPY $rdi
+ %1:_(s64) = COPY $rsi
+ %2:_(s64) = G_SREM %0, %1
+ $rax = COPY %2(s64)
+ RET 0, implicit $rax
+
+...
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-legalize-udiv.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-legalize-udiv.mir?rev=343966&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-legalize-udiv.mir (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-legalize-udiv.mir Mon Oct 8 06:40:34 2018
@@ -0,0 +1,253 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+ ; ModuleID = 'udiv.ll'
+ source_filename = "udiv.ll"
+ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+ define i8 @test_udiv_i8(i8 %arg1, i8 %arg2) {
+ %res = udiv i8 %arg1, %arg2
+ ret i8 %res
+ }
+
+ define i16 @test_udiv_i16(i16 %arg1, i16 %arg2) {
+ %res = udiv i16 %arg1, %arg2
+ ret i16 %res
+ }
+
+ define i32 @test_udiv_i32(i32 %arg1, i32 %arg2) {
+ %res = udiv i32 %arg1, %arg2
+ ret i32 %res
+ }
+
+ define i64 @test_udiv_i64(i64 %arg1, i64 %arg2) {
+ %res = udiv i64 %arg1, %arg2
+ ret i64 %res
+ }
+
+...
+---
+name: test_udiv_i8
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+ - { id: 3, class: _, preferred-register: '' }
+ - { id: 4, class: _, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $edi, $esi
+
+ ; CHECK-LABEL: name: test_udiv_i8
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
+ ; CHECK: [[UDIV:%[0-9]+]]:_(s8) = G_UDIV [[TRUNC]], [[TRUNC1]]
+ ; CHECK: $al = COPY [[UDIV]](s8)
+ ; CHECK: RET 0, implicit $al
+ %2:_(s32) = COPY $edi
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:_(s32) = COPY $esi
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_UDIV %0, %1
+ $al = COPY %4(s8)
+ RET 0, implicit $al
+
+...
+---
+name: test_udiv_i16
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+ - { id: 3, class: _, preferred-register: '' }
+ - { id: 4, class: _, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $edi, $esi
+
+ ; CHECK-LABEL: name: test_udiv_i16
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK: [[UDIV:%[0-9]+]]:_(s16) = G_UDIV [[TRUNC]], [[TRUNC1]]
+ ; CHECK: $ax = COPY [[UDIV]](s16)
+ ; CHECK: RET 0, implicit $ax
+ %2:_(s32) = COPY $edi
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:_(s32) = COPY $esi
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_UDIV %0, %1
+ $ax = COPY %4(s16)
+ RET 0, implicit $ax
+
+...
+---
+name: test_udiv_i32
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $edi, $esi
+
+ ; CHECK-LABEL: name: test_udiv_i32
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
+ ; CHECK: [[UDIV:%[0-9]+]]:_(s32) = G_UDIV [[COPY]], [[COPY1]]
+ ; CHECK: $eax = COPY [[UDIV]](s32)
+ ; CHECK: RET 0, implicit $eax
+ %0:_(s32) = COPY $edi
+ %1:_(s32) = COPY $esi
+ %2:_(s32) = G_UDIV %0, %1
+ $eax = COPY %2(s32)
+ RET 0, implicit $eax
+
+...
+---
+name: test_udiv_i64
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $rdi, $rsi
+
+ ; CHECK-LABEL: name: test_udiv_i64
+ ; CHECK: liveins: $rdi, $rsi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi
+ ; CHECK: [[UDIV:%[0-9]+]]:_(s64) = G_UDIV [[COPY]], [[COPY1]]
+ ; CHECK: $rax = COPY [[UDIV]](s64)
+ ; CHECK: RET 0, implicit $rax
+ %0:_(s64) = COPY $rdi
+ %1:_(s64) = COPY $rsi
+ %2:_(s64) = G_UDIV %0, %1
+ $rax = COPY %2(s64)
+ RET 0, implicit $rax
+
+...
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-legalize-urem.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-legalize-urem.mir?rev=343966&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-legalize-urem.mir (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-legalize-urem.mir Mon Oct 8 06:40:34 2018
@@ -0,0 +1,253 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+ ; ModuleID = 'urem.ll'
+ source_filename = "urem.ll"
+ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+ define i8 @test_urem_i8(i8 %arg1, i8 %arg2) {
+ %res = urem i8 %arg1, %arg2
+ ret i8 %res
+ }
+
+ define i16 @test_urem_i16(i16 %arg1, i16 %arg2) {
+ %res = urem i16 %arg1, %arg2
+ ret i16 %res
+ }
+
+ define i32 @test_urem_i32(i32 %arg1, i32 %arg2) {
+ %res = urem i32 %arg1, %arg2
+ ret i32 %res
+ }
+
+ define i64 @test_urem_i64(i64 %arg1, i64 %arg2) {
+ %res = urem i64 %arg1, %arg2
+ ret i64 %res
+ }
+
+...
+---
+name: test_urem_i8
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+ - { id: 3, class: _, preferred-register: '' }
+ - { id: 4, class: _, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $edi, $esi
+
+ ; CHECK-LABEL: name: test_urem_i8
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
+ ; CHECK: [[UREM:%[0-9]+]]:_(s8) = G_UREM [[TRUNC]], [[TRUNC1]]
+ ; CHECK: $al = COPY [[UREM]](s8)
+ ; CHECK: RET 0, implicit $al
+ %2:_(s32) = COPY $edi
+ %0:_(s8) = G_TRUNC %2(s32)
+ %3:_(s32) = COPY $esi
+ %1:_(s8) = G_TRUNC %3(s32)
+ %4:_(s8) = G_UREM %0, %1
+ $al = COPY %4(s8)
+ RET 0, implicit $al
+
+...
+---
+name: test_urem_i16
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+ - { id: 3, class: _, preferred-register: '' }
+ - { id: 4, class: _, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $edi, $esi
+
+ ; CHECK-LABEL: name: test_urem_i16
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
+ ; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
+ ; CHECK: [[UREM:%[0-9]+]]:_(s16) = G_UREM [[TRUNC]], [[TRUNC1]]
+ ; CHECK: $ax = COPY [[UREM]](s16)
+ ; CHECK: RET 0, implicit $ax
+ %2:_(s32) = COPY $edi
+ %0:_(s16) = G_TRUNC %2(s32)
+ %3:_(s32) = COPY $esi
+ %1:_(s16) = G_TRUNC %3(s32)
+ %4:_(s16) = G_UREM %0, %1
+ $ax = COPY %4(s16)
+ RET 0, implicit $ax
+
+...
+---
+name: test_urem_i32
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $edi, $esi
+
+ ; CHECK-LABEL: name: test_urem_i32
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
+ ; CHECK: [[UREM:%[0-9]+]]:_(s32) = G_UREM [[COPY]], [[COPY1]]
+ ; CHECK: $eax = COPY [[UREM]](s32)
+ ; CHECK: RET 0, implicit $eax
+ %0:_(s32) = COPY $edi
+ %1:_(s32) = COPY $esi
+ %2:_(s32) = G_UREM %0, %1
+ $eax = COPY %2(s32)
+ RET 0, implicit $eax
+
+...
+---
+name: test_urem_i64
+alignment: 4
+exposesReturnsTwice: false
+legalized: false
+regBankSelected: false
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: _, preferred-register: '' }
+ - { id: 1, class: _, preferred-register: '' }
+ - { id: 2, class: _, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $rdi, $rsi
+
+ ; CHECK-LABEL: name: test_urem_i64
+ ; CHECK: liveins: $rdi, $rsi
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
+ ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi
+ ; CHECK: [[UREM:%[0-9]+]]:_(s64) = G_UREM [[COPY]], [[COPY1]]
+ ; CHECK: $rax = COPY [[UREM]](s64)
+ ; CHECK: RET 0, implicit $rax
+ %0:_(s64) = COPY $rdi
+ %1:_(s64) = COPY $rsi
+ %2:_(s64) = G_UREM %0, %1
+ $rax = COPY %2(s64)
+ RET 0, implicit $rax
+
+...
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir?rev=343966&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir Mon Oct 8 06:40:34 2018
@@ -0,0 +1,264 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+ ; ModuleID = 'srem.ll'
+ source_filename = "srem.ll"
+ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+ define i8 @test_srem_i8(i8 %arg1, i8 %arg2) {
+ %res = srem i8 %arg1, %arg2
+ ret i8 %res
+ }
+
+ define i16 @test_srem_i16(i16 %arg1, i16 %arg2) {
+ %res = srem i16 %arg1, %arg2
+ ret i16 %res
+ }
+
+ define i32 @test_srem_i32(i32 %arg1, i32 %arg2) {
+ %res = srem i32 %arg1, %arg2
+ ret i32 %res
+ }
+
+ define i64 @test_srem_i64(i64 %arg1, i64 %arg2) {
+ %res = srem i64 %arg1, %arg2
+ ret i64 %res
+ }
+
+...
+---
+name: test_srem_i8
+alignment: 4
+exposesReturnsTwice: false
+legalized: true
+regBankSelected: true
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr, preferred-register: '' }
+ - { id: 1, class: gpr, preferred-register: '' }
+ - { id: 2, class: gpr, preferred-register: '' }
+ - { id: 3, class: gpr, preferred-register: '' }
+ - { id: 4, class: gpr, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $edi, $esi
+
+ ; CHECK-LABEL: name: test_srem_i8
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+ ; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
+ ; CHECK: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY2]].sub_8bit
+ ; CHECK: $ax = MOVSX16rr8 [[COPY1]]
+ ; CHECK: IDIV8r [[COPY3]], implicit-def $al, implicit-def $ah, implicit-def $eflags, implicit $ax
+ ; CHECK: [[COPY4:%[0-9]+]]:gr8 = COPY $ah
+ ; CHECK: $al = COPY [[COPY4]]
+ ; CHECK: RET 0, implicit $al
+ %2:gpr(s32) = COPY $edi
+ %0:gpr(s8) = G_TRUNC %2(s32)
+ %3:gpr(s32) = COPY $esi
+ %1:gpr(s8) = G_TRUNC %3(s32)
+ %4:gpr(s8) = G_SREM %0, %1
+ $al = COPY %4(s8)
+ RET 0, implicit $al
+
+...
+---
+name: test_srem_i16
+alignment: 4
+exposesReturnsTwice: false
+legalized: true
+regBankSelected: true
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr, preferred-register: '' }
+ - { id: 1, class: gpr, preferred-register: '' }
+ - { id: 2, class: gpr, preferred-register: '' }
+ - { id: 3, class: gpr, preferred-register: '' }
+ - { id: 4, class: gpr, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $edi, $esi
+
+ ; CHECK-LABEL: name: test_srem_i16
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
+ ; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
+ ; CHECK: [[COPY3:%[0-9]+]]:gr16 = COPY [[COPY2]].sub_16bit
+ ; CHECK: $ax = COPY [[COPY1]]
+ ; CHECK: CWD implicit-def $ax, implicit-def $dx, implicit $ax
+ ; CHECK: IDIV16r [[COPY3]], implicit-def $ax, implicit-def $dx, implicit-def $eflags, implicit $ax, implicit $dx
+ ; CHECK: [[COPY4:%[0-9]+]]:gr16 = COPY $dx
+ ; CHECK: $ax = COPY [[COPY4]]
+ ; CHECK: RET 0, implicit $ax
+ %2:gpr(s32) = COPY $edi
+ %0:gpr(s16) = G_TRUNC %2(s32)
+ %3:gpr(s32) = COPY $esi
+ %1:gpr(s16) = G_TRUNC %3(s32)
+ %4:gpr(s16) = G_SREM %0, %1
+ $ax = COPY %4(s16)
+ RET 0, implicit $ax
+
+...
+---
+name: test_srem_i32
+alignment: 4
+exposesReturnsTwice: false
+legalized: true
+regBankSelected: true
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr, preferred-register: '' }
+ - { id: 1, class: gpr, preferred-register: '' }
+ - { id: 2, class: gpr, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $edi, $esi
+
+ ; CHECK-LABEL: name: test_srem_i32
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+ ; CHECK: $eax = COPY [[COPY]]
+ ; CHECK: CDQ implicit-def $eax, implicit-def $edx, implicit $eax
+ ; CHECK: IDIV32r [[COPY1]], implicit-def $eax, implicit-def $edx, implicit-def $eflags, implicit $eax, implicit $edx
+ ; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $edx
+ ; CHECK: $eax = COPY [[COPY2]]
+ ; CHECK: RET 0, implicit $eax
+ %0:gpr(s32) = COPY $edi
+ %1:gpr(s32) = COPY $esi
+ %2:gpr(s32) = G_SREM %0, %1
+ $eax = COPY %2(s32)
+ RET 0, implicit $eax
+
+...
+---
+name: test_srem_i64
+alignment: 4
+exposesReturnsTwice: false
+legalized: true
+regBankSelected: true
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr, preferred-register: '' }
+ - { id: 1, class: gpr, preferred-register: '' }
+ - { id: 2, class: gpr, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $rdi, $rsi
+
+ ; CHECK-LABEL: name: test_srem_i64
+ ; CHECK: liveins: $rdi, $rsi
+ ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; CHECK: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; CHECK: $rax = COPY [[COPY]]
+ ; CHECK: CQO implicit-def $rax, implicit-def $rdx, implicit $rax
+ ; CHECK: IDIV64r [[COPY1]], implicit-def $rax, implicit-def $rdx, implicit-def $eflags, implicit $rax, implicit $rdx
+ ; CHECK: [[COPY2:%[0-9]+]]:gr64 = COPY $rdx
+ ; CHECK: $rax = COPY [[COPY2]]
+ ; CHECK: RET 0, implicit $rax
+ %0:gpr(s64) = COPY $rdi
+ %1:gpr(s64) = COPY $rsi
+ %2:gpr(s64) = G_SREM %0, %1
+ $rax = COPY %2(s64)
+ RET 0, implicit $rax
+
+...
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-select-udiv.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-select-udiv.mir?rev=343966&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-select-udiv.mir (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-select-udiv.mir Mon Oct 8 06:40:34 2018
@@ -0,0 +1,267 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+ ; ModuleID = 'udiv.ll'
+ source_filename = "udiv.ll"
+ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+ define i8 @test_udiv_i8(i8 %arg1, i8 %arg2) {
+ %res = udiv i8 %arg1, %arg2
+ ret i8 %res
+ }
+
+ define i16 @test_udiv_i16(i16 %arg1, i16 %arg2) {
+ %res = udiv i16 %arg1, %arg2
+ ret i16 %res
+ }
+
+ define i32 @test_udiv_i32(i32 %arg1, i32 %arg2) {
+ %res = udiv i32 %arg1, %arg2
+ ret i32 %res
+ }
+
+ define i64 @test_udiv_i64(i64 %arg1, i64 %arg2) {
+ %res = udiv i64 %arg1, %arg2
+ ret i64 %res
+ }
+
+...
+---
+name: test_udiv_i8
+alignment: 4
+exposesReturnsTwice: false
+legalized: true
+regBankSelected: true
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr, preferred-register: '' }
+ - { id: 1, class: gpr, preferred-register: '' }
+ - { id: 2, class: gpr, preferred-register: '' }
+ - { id: 3, class: gpr, preferred-register: '' }
+ - { id: 4, class: gpr, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $edi, $esi
+
+ ; CHECK-LABEL: name: test_udiv_i8
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+ ; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
+ ; CHECK: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY2]].sub_8bit
+ ; CHECK: $ax = MOVZX16rr8 [[COPY1]]
+ ; CHECK: DIV8r [[COPY3]], implicit-def $al, implicit-def $ah, implicit-def $eflags, implicit $ax
+ ; CHECK: [[COPY4:%[0-9]+]]:gr8 = COPY $al
+ ; CHECK: $al = COPY [[COPY4]]
+ ; CHECK: RET 0, implicit $al
+ %2:gpr(s32) = COPY $edi
+ %0:gpr(s8) = G_TRUNC %2(s32)
+ %3:gpr(s32) = COPY $esi
+ %1:gpr(s8) = G_TRUNC %3(s32)
+ %4:gpr(s8) = G_UDIV %0, %1
+ $al = COPY %4(s8)
+ RET 0, implicit $al
+
+...
+---
+name: test_udiv_i16
+alignment: 4
+exposesReturnsTwice: false
+legalized: true
+regBankSelected: true
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr, preferred-register: '' }
+ - { id: 1, class: gpr, preferred-register: '' }
+ - { id: 2, class: gpr, preferred-register: '' }
+ - { id: 3, class: gpr, preferred-register: '' }
+ - { id: 4, class: gpr, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $edi, $esi
+
+ ; CHECK-LABEL: name: test_udiv_i16
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
+ ; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
+ ; CHECK: [[COPY3:%[0-9]+]]:gr16 = COPY [[COPY2]].sub_16bit
+ ; CHECK: $ax = COPY [[COPY1]]
+ ; CHECK: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+ ; CHECK: $dx = COPY [[MOV32r0_]].sub_16bit
+ ; CHECK: DIV16r [[COPY3]], implicit-def $ax, implicit-def $dx, implicit-def $eflags, implicit $ax, implicit $dx
+ ; CHECK: [[COPY4:%[0-9]+]]:gr16 = COPY $ax
+ ; CHECK: $ax = COPY [[COPY4]]
+ ; CHECK: RET 0, implicit $ax
+ %2:gpr(s32) = COPY $edi
+ %0:gpr(s16) = G_TRUNC %2(s32)
+ %3:gpr(s32) = COPY $esi
+ %1:gpr(s16) = G_TRUNC %3(s32)
+ %4:gpr(s16) = G_UDIV %0, %1
+ $ax = COPY %4(s16)
+ RET 0, implicit $ax
+
+...
+---
+name: test_udiv_i32
+alignment: 4
+exposesReturnsTwice: false
+legalized: true
+regBankSelected: true
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr, preferred-register: '' }
+ - { id: 1, class: gpr, preferred-register: '' }
+ - { id: 2, class: gpr, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $edi, $esi
+
+ ; CHECK-LABEL: name: test_udiv_i32
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+ ; CHECK: $eax = COPY [[COPY]]
+ ; CHECK: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+ ; CHECK: $edx = COPY [[MOV32r0_]]
+ ; CHECK: DIV32r [[COPY1]], implicit-def $eax, implicit-def $edx, implicit-def $eflags, implicit $eax, implicit $edx
+ ; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $eax
+ ; CHECK: $eax = COPY [[COPY2]]
+ ; CHECK: RET 0, implicit $eax
+ %0:gpr(s32) = COPY $edi
+ %1:gpr(s32) = COPY $esi
+ %2:gpr(s32) = G_UDIV %0, %1
+ $eax = COPY %2(s32)
+ RET 0, implicit $eax
+
+...
+---
+name: test_udiv_i64
+alignment: 4
+exposesReturnsTwice: false
+legalized: true
+regBankSelected: true
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr, preferred-register: '' }
+ - { id: 1, class: gpr, preferred-register: '' }
+ - { id: 2, class: gpr, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $rdi, $rsi
+
+ ; CHECK-LABEL: name: test_udiv_i64
+ ; CHECK: liveins: $rdi, $rsi
+ ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; CHECK: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; CHECK: $rax = COPY [[COPY]]
+ ; CHECK: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+ ; CHECK: $rdx = SUBREG_TO_REG 0, [[MOV32r0_]], %subreg.sub_32bit
+ ; CHECK: DIV64r [[COPY1]], implicit-def $rax, implicit-def $rdx, implicit-def $eflags, implicit $rax, implicit $rdx
+ ; CHECK: [[COPY2:%[0-9]+]]:gr64 = COPY $rax
+ ; CHECK: $rax = COPY [[COPY2]]
+ ; CHECK: RET 0, implicit $rax
+ %0:gpr(s64) = COPY $rdi
+ %1:gpr(s64) = COPY $rsi
+ %2:gpr(s64) = G_UDIV %0, %1
+ $rax = COPY %2(s64)
+ RET 0, implicit $rax
+
+...
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir?rev=343966&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir Mon Oct 8 06:40:34 2018
@@ -0,0 +1,267 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
+
+--- |
+ ; ModuleID = 'urem.ll'
+ source_filename = "urem.ll"
+ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+ define i8 @test_urem_i8(i8 %arg1, i8 %arg2) {
+ %res = urem i8 %arg1, %arg2
+ ret i8 %res
+ }
+
+ define i16 @test_urem_i16(i16 %arg1, i16 %arg2) {
+ %res = urem i16 %arg1, %arg2
+ ret i16 %res
+ }
+
+ define i32 @test_urem_i32(i32 %arg1, i32 %arg2) {
+ %res = urem i32 %arg1, %arg2
+ ret i32 %res
+ }
+
+ define i64 @test_urem_i64(i64 %arg1, i64 %arg2) {
+ %res = urem i64 %arg1, %arg2
+ ret i64 %res
+ }
+
+...
+---
+name: test_urem_i8
+alignment: 4
+exposesReturnsTwice: false
+legalized: true
+regBankSelected: true
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr, preferred-register: '' }
+ - { id: 1, class: gpr, preferred-register: '' }
+ - { id: 2, class: gpr, preferred-register: '' }
+ - { id: 3, class: gpr, preferred-register: '' }
+ - { id: 4, class: gpr, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $edi, $esi
+
+ ; CHECK-LABEL: name: test_urem_i8
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+ ; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
+ ; CHECK: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY2]].sub_8bit
+ ; CHECK: $ax = MOVZX16rr8 [[COPY1]]
+ ; CHECK: DIV8r [[COPY3]], implicit-def $al, implicit-def $ah, implicit-def $eflags, implicit $ax
+ ; CHECK: [[COPY4:%[0-9]+]]:gr8 = COPY $ah
+ ; CHECK: $al = COPY [[COPY4]]
+ ; CHECK: RET 0, implicit $al
+ %2:gpr(s32) = COPY $edi
+ %0:gpr(s8) = G_TRUNC %2(s32)
+ %3:gpr(s32) = COPY $esi
+ %1:gpr(s8) = G_TRUNC %3(s32)
+ %4:gpr(s8) = G_UREM %0, %1
+ $al = COPY %4(s8)
+ RET 0, implicit $al
+
+...
+---
+name: test_urem_i16
+alignment: 4
+exposesReturnsTwice: false
+legalized: true
+regBankSelected: true
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr, preferred-register: '' }
+ - { id: 1, class: gpr, preferred-register: '' }
+ - { id: 2, class: gpr, preferred-register: '' }
+ - { id: 3, class: gpr, preferred-register: '' }
+ - { id: 4, class: gpr, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $edi, $esi
+
+ ; CHECK-LABEL: name: test_urem_i16
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
+ ; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
+ ; CHECK: [[COPY3:%[0-9]+]]:gr16 = COPY [[COPY2]].sub_16bit
+ ; CHECK: $ax = COPY [[COPY1]]
+ ; CHECK: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+ ; CHECK: $dx = COPY [[MOV32r0_]].sub_16bit
+ ; CHECK: DIV16r [[COPY3]], implicit-def $ax, implicit-def $dx, implicit-def $eflags, implicit $ax, implicit $dx
+ ; CHECK: [[COPY4:%[0-9]+]]:gr16 = COPY $dx
+ ; CHECK: $ax = COPY [[COPY4]]
+ ; CHECK: RET 0, implicit $ax
+ %2:gpr(s32) = COPY $edi
+ %0:gpr(s16) = G_TRUNC %2(s32)
+ %3:gpr(s32) = COPY $esi
+ %1:gpr(s16) = G_TRUNC %3(s32)
+ %4:gpr(s16) = G_UREM %0, %1
+ $ax = COPY %4(s16)
+ RET 0, implicit $ax
+
+...
+---
+name: test_urem_i32
+alignment: 4
+exposesReturnsTwice: false
+legalized: true
+regBankSelected: true
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr, preferred-register: '' }
+ - { id: 1, class: gpr, preferred-register: '' }
+ - { id: 2, class: gpr, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $edi, $esi
+
+ ; CHECK-LABEL: name: test_urem_i32
+ ; CHECK: liveins: $edi, $esi
+ ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+ ; CHECK: $eax = COPY [[COPY]]
+ ; CHECK: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+ ; CHECK: $edx = COPY [[MOV32r0_]]
+ ; CHECK: DIV32r [[COPY1]], implicit-def $eax, implicit-def $edx, implicit-def $eflags, implicit $eax, implicit $edx
+ ; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $edx
+ ; CHECK: $eax = COPY [[COPY2]]
+ ; CHECK: RET 0, implicit $eax
+ %0:gpr(s32) = COPY $edi
+ %1:gpr(s32) = COPY $esi
+ %2:gpr(s32) = G_UREM %0, %1
+ $eax = COPY %2(s32)
+ RET 0, implicit $eax
+
+...
+---
+name: test_urem_i64
+alignment: 4
+exposesReturnsTwice: false
+legalized: true
+regBankSelected: true
+selected: false
+failedISel: false
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr, preferred-register: '' }
+ - { id: 1, class: gpr, preferred-register: '' }
+ - { id: 2, class: gpr, preferred-register: '' }
+liveins:
+frameInfo:
+ isFrameAddressTaken: false
+ isReturnAddressTaken: false
+ hasStackMap: false
+ hasPatchPoint: false
+ stackSize: 0
+ offsetAdjustment: 0
+ maxAlignment: 0
+ adjustsStack: false
+ hasCalls: false
+ stackProtector: ''
+ maxCallFrameSize: 4294967295
+ hasOpaqueSPAdjustment: false
+ hasVAStart: false
+ hasMustTailInVarArgFunc: false
+ localFrameSize: 0
+ savePoint: ''
+ restorePoint: ''
+fixedStack:
+stack:
+constants:
+body: |
+ bb.1 (%ir-block.0):
+ liveins: $rdi, $rsi
+
+ ; CHECK-LABEL: name: test_urem_i64
+ ; CHECK: liveins: $rdi, $rsi
+ ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; CHECK: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; CHECK: $rax = COPY [[COPY]]
+ ; CHECK: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+ ; CHECK: $rdx = SUBREG_TO_REG 0, [[MOV32r0_]], %subreg.sub_32bit
+ ; CHECK: DIV64r [[COPY1]], implicit-def $rax, implicit-def $rdx, implicit-def $eflags, implicit $rax, implicit $rdx
+ ; CHECK: [[COPY2:%[0-9]+]]:gr64 = COPY $rdx
+ ; CHECK: $rax = COPY [[COPY2]]
+ ; CHECK: RET 0, implicit $rax
+ %0:gpr(s64) = COPY $rdi
+ %1:gpr(s64) = COPY $rsi
+ %2:gpr(s64) = G_UREM %0, %1
+ $rax = COPY %2(s64)
+ RET 0, implicit $rax
+
+...
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