[PATCH] D52975: [TargetLowering][RISCV] Introduce getExtendForShiftAmount and implement for RISC-V

[Alex Bradbury via Phabricator via llvm-commits]

asb created this revision.
asb added reviewers: eli.friedman, bogner, spatel.
Herald added subscribers: jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, mgrang, edward-jones, zzheng, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar.

As of https://reviews.llvm.org/rL125457, the shift amount operand is always zero-extended when being promoted. This is conservatively safe, but on some targets (e.g. RISC-V) this leads to unnecessary instructions as the native shift operations ignore all but the lower 5/6 bits.

This patch introduces the getExtendForShiftAmount hook which is called from SelectionDAGBuilder::visitShift and implements that hook for RISC-V. The benefit can be seen in the promoted 8 and 16-bit shifts in the test/CodeGen/alu{8,16}.ll test cases.


https://reviews.llvm.org/D52975

Files:
  include/llvm/CodeGen/TargetLowering.h
  lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  test/CodeGen/RISCV/alu16.ll
  test/CodeGen/RISCV/alu8.ll

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