[llvm] r343940 - [DAGCombiner] allow undef elts in vector fabs/fneg matching

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Sun Oct  7 08:32:06 2018
New Revision: 343940

URL: http://llvm.org/viewvc/llvm-project?rev=343940&view=rev
Log:
[DAGCombiner] allow undef elts in vector fabs/fneg matching

This change is proposed as a part of D44548, but we
need this independently to avoid regressions from improved
undef propagation in SimplifyDemandedVectorElts().

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/test/CodeGen/X86/fp-logic.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=343940&r1=343939&r2=343940&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Sun Oct  7 08:32:06 2018
@@ -9851,7 +9851,7 @@ static SDValue foldBitcastedFPLogic(SDNo
   // Fold (bitcast int (and (bitcast fp X to int), 0x7fff...) to fp) -> fabs X
   // Fold (bitcast int (xor (bitcast fp X to int), 0x8000...) to fp) -> fneg X
   SDValue LogicOp0 = N0.getOperand(0);
-  ConstantSDNode *LogicOp1 = isConstOrConstSplat(N0.getOperand(1));
+  ConstantSDNode *LogicOp1 = isConstOrConstSplat(N0.getOperand(1), true);
   if (LogicOp1 && LogicOp1->getAPIntValue() == SignMask &&
       LogicOp0.getOpcode() == ISD::BITCAST &&
       LogicOp0.getOperand(0).getValueType() == VT)

Modified: llvm/trunk/test/CodeGen/X86/fp-logic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fp-logic.ll?rev=343940&r1=343939&r2=343940&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fp-logic.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fp-logic.ll Sun Oct  7 08:32:06 2018
@@ -323,8 +323,7 @@ define <4 x float> @fadd_bitcast_fneg_ve
 define <4 x float> @fadd_bitcast_fneg_vec_undef_elts(<4 x float> %x, <4 x float> %y) {
 ; CHECK-LABEL: fadd_bitcast_fneg_vec_undef_elts:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xorps {{.*}}(%rip), %xmm1
-; CHECK-NEXT:    addps %xmm1, %xmm0
+; CHECK-NEXT:    subps %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %bc1 = bitcast <4 x float> %y to <4 x i32>
   %xor = xor <4 x i32> %bc1, <i32 2147483648, i32 2147483648, i32 undef, i32 2147483648>
@@ -345,11 +344,10 @@ define <4 x float> @fsub_bitcast_fneg_ve
   ret <4 x float> %fsub
 }
 
-define <4 x float> @fsub_bitcast_fneg_vec_elts(<4 x float> %x, <4 x float> %y) {
-; CHECK-LABEL: fsub_bitcast_fneg_vec_elts:
+define <4 x float> @fsub_bitcast_fneg_vec_undef_elts(<4 x float> %x, <4 x float> %y) {
+; CHECK-LABEL: fsub_bitcast_fneg_vec_undef_elts:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xorps {{.*}}(%rip), %xmm1
-; CHECK-NEXT:    subps %xmm1, %xmm0
+; CHECK-NEXT:    addps %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %bc1 = bitcast <4 x float> %y to <4 x i32>
   %xor = xor <4 x i32> %bc1, <i32 undef, i32 2147483648, i32 undef, i32 2147483648>