[llvm] r343938 - [x86] add tests for FP logic folding for vectors with undefs; NFC

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Sun Oct  7 08:05:39 2018
New Revision: 343938

URL: http://llvm.org/viewvc/llvm-project?rev=343938&view=rev
Log:
[x86] add tests for FP logic folding for vectors with undefs; NFC 

Modified:
    llvm/trunk/test/CodeGen/X86/fp-logic.ll

Modified: llvm/trunk/test/CodeGen/X86/fp-logic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fp-logic.ll?rev=343938&r1=343937&r2=343938&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fp-logic.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fp-logic.ll Sun Oct  7 08:05:39 2018
@@ -320,6 +320,19 @@ define <4 x float> @fadd_bitcast_fneg_ve
   ret <4 x float> %fadd
 }
 
+define <4 x float> @fadd_bitcast_fneg_vec_undef_elts(<4 x float> %x, <4 x float> %y) {
+; CHECK-LABEL: fadd_bitcast_fneg_vec_undef_elts:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorps {{.*}}(%rip), %xmm1
+; CHECK-NEXT:    addps %xmm1, %xmm0
+; CHECK-NEXT:    retq
+  %bc1 = bitcast <4 x float> %y to <4 x i32>
+  %xor = xor <4 x i32> %bc1, <i32 2147483648, i32 2147483648, i32 undef, i32 2147483648>
+  %bc2 = bitcast <4 x i32> %xor to <4 x float>
+  %fadd = fadd <4 x float> %x, %bc2
+  ret <4 x float> %fadd
+}
+
 define <4 x float> @fsub_bitcast_fneg_vec(<4 x float> %x, <4 x float> %y) {
 ; CHECK-LABEL: fsub_bitcast_fneg_vec:
 ; CHECK:       # %bb.0:
@@ -330,6 +343,19 @@ define <4 x float> @fsub_bitcast_fneg_ve
   %bc2 = bitcast <4 x i32> %xor to <4 x float>
   %fsub = fsub <4 x float> %x, %bc2
   ret <4 x float> %fsub
+}
+
+define <4 x float> @fsub_bitcast_fneg_vec_elts(<4 x float> %x, <4 x float> %y) {
+; CHECK-LABEL: fsub_bitcast_fneg_vec_elts:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorps {{.*}}(%rip), %xmm1
+; CHECK-NEXT:    subps %xmm1, %xmm0
+; CHECK-NEXT:    retq
+  %bc1 = bitcast <4 x float> %y to <4 x i32>
+  %xor = xor <4 x i32> %bc1, <i32 undef, i32 2147483648, i32 undef, i32 2147483648>
+  %bc2 = bitcast <4 x i32> %xor to <4 x float>
+  %fsub = fsub <4 x float> %x, %bc2
+  ret <4 x float> %fsub
 }
 
 define <4 x float> @fadd_bitcast_fneg_vec_width(<4 x float> %x, <4 x float> %y) {