[PATCH] D49671: [SchedModel] Propagate read advance cycles to implicit operands outside instruction descriptor

[Jonas Paulsson via Phabricator via llvm-commits]

jonpa requested review of this revision.
jonpa added reviewers: tstellar, rampitec, RKSimon.
jonpa added a comment.

I tried to begin with the test updating, but found that at least the AMDGPU tests had a lot of repeated patterns, which I suspect isn't that much work if you know the assembly dialect, but for me it was easy to get lost.

Since this is a general improvement for any target that cares about operand read advances, I would like to ask if someone from each target please could apply the patch and do the test updating? Just mail me a patch and I'll apply it and put it up here.

I am not sure about the general agreement on test updating, but I think personally this makes collaborative sense, or?

  LLVM :: CodeGen/AMDGPU/call-argument-types.ll
  LLVM :: CodeGen/AMDGPU/call-preserved-registers.ll
  LLVM :: CodeGen/AMDGPU/callee-special-input-sgprs.ll
  LLVM :: CodeGen/AMDGPU/indirect-addressing-si.ll
  LLVM :: CodeGen/AMDGPU/inline-asm.ll
  LLVM :: CodeGen/AMDGPU/insert_vector_elt.ll
  LLVM :: CodeGen/AMDGPU/misched-killflags.mir
  LLVM :: CodeGen/AMDGPU/nested-calls.ll
  LLVM :: CodeGen/AMDGPU/undefined-subreg-liverange.ll
  LLVM :: CodeGen/ARM/Windows/chkstk-movw-movt-isel.ll
  LLVM :: CodeGen/ARM/Windows/chkstk.ll
  LLVM :: CodeGen/ARM/Windows/memset.ll
  LLVM :: CodeGen/ARM/arm-and-tst-peephole.ll
  LLVM :: CodeGen/ARM/arm-shrink-wrapping.ll
  LLVM :: CodeGen/ARM/cortex-a57-misched-ldm-wrback.ll
  LLVM :: CodeGen/ARM/cortex-a57-misched-ldm.ll
  LLVM :: CodeGen/ARM/cortex-a57-misched-vldm-wrback.ll
  LLVM :: CodeGen/ARM/cortex-a57-misched-vldm.ll
  LLVM :: CodeGen/ARM/fp16-instructions.ll
  LLVM :: CodeGen/ARM/select.ll
  LLVM :: CodeGen/ARM/twoaddrinstr.ll
  LLVM :: CodeGen/ARM/vcombine.ll
  LLVM :: CodeGen/ARM/vuzp.ll
  LLVM :: CodeGen/Hexagon/ps_call_nr.ll
  LLVM :: CodeGen/Thumb2/umulo-128-legalisation-lowering.ll
  LLVM :: CodeGen/Thumb2/umulo-64-legalisation-lowering.ll
  LLVM :: CodeGen/X86/lsr-loop-exit-cond.ll
  LLVM :: CodeGen/X86/phys-reg-local-regalloc.ll
  LLVM :: CodeGen/X86/schedule-x86-64-shld.ll
  LLVM :: CodeGen/X86/schedule-x86_32.ll


https://reviews.llvm.org/D49671