[PATCH] D49671: [SchedModel] Propagate read advance cycles to implicit operands outside instruction descriptor

[Matthias Braun via Phabricator via llvm-commits]

MatzeB accepted this revision.
MatzeB added a comment.
This revision is now accepted and ready to land.

Sorry for slow response. LGTM, some nitpicks below but feel free to fix testcases and nitpicks at your own discretion.



================
Comment at: lib/CodeGen/ScheduleDAGInstrs.cpp:240-241
+  const MCInstrDesc *DefMIDesc = &SU->getInstr()->getDesc();
+  bool DescriptorDef = (OperIdx < DefMIDesc->getNumOperands() ||
+                        DefMIDesc->hasImplicitDefOfPhysReg(MO.getReg()));
   for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
----------------
How about reversing the condition and calling this:
```
bool ImplicitPseudoDef = (OperIdx >= DefMIDesc->getNumOperands() &&
                          !DefMIDesc->hasImplicitDefOfPhysReg(MO.getReg()));
```


================
Comment at: lib/CodeGen/ScheduleDAGInstrs.cpp:267-269
+      bool DescriptorUse =
+          (!UseMIDesc || (UseOp < UseMIDesc->getNumOperands() ||
+                          UseMIDesc->hasImplicitUseOfPhysReg(*Alias)));
----------------
similar here:
```
bool ImplicitPseudoUse = UseMIDesc && UseOp >= UseMIDesc->getNumOperands() && !UseMIDesc->hasImplicitUseOfPhysReg(*Alias);
```


================
Comment at: test/CodeGen/SystemZ/misched-readadvances.mir:1
+# Check that the latency adjustment (ReadAdvance) for the MSY register operand
+# is also used on the extra operand for the full register added by RegAlloc.
----------------
If you have the time look at: https://llvm.org/docs/MIRLangRef.html#simplifying-mir-files

This smells like you can do things like dropping the IR part, not listing the successor blocks (at least for the blocks that don't use the jumptable)...


https://reviews.llvm.org/D49671