[PATCH] D52946: AMDGPU: Add support pattern for SUB of one bit

[Changpeng Fang via Phabricator via llvm-commits]

cfang created this revision.
cfang added reviewers: rampitec, arsenm.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.

Add selection patterns to support one bit Sub.


https://reviews.llvm.org/D52946

Files:
  lib/Target/AMDGPU/SIInstructions.td
  test/CodeGen/AMDGPU/sub_i1.ll


Index: test/CodeGen/AMDGPU/sub_i1.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/sub_i1.ll
@@ -0,0 +1,21 @@
+; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+
+
+; GCN-LABEL: {{^}}sub_var_var_i1:
+; GCN: s_xor_b64
+define amdgpu_kernel void @sub_var_var_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in0, i1 addrspace(1)* %in1) {
+  %a = load volatile i1, i1 addrspace(1)* %in0
+  %b = load volatile i1, i1 addrspace(1)* %in1
+  %sub = sub i1 %a, %b
+  store i1 %sub, i1 addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}sub_var_imm_i1:
+; GCN: s_not_b64
+define amdgpu_kernel void @sub_var_imm_i1(i1 addrspace(1)* %out, i1 addrspace(1)* %in) {
+  %a = load volatile i1, i1 addrspace(1)* %in
+  %sub = sub i1 %a, 1
+  store i1 %sub, i1 addrspace(1)* %out
+  ret void
+}
Index: lib/Target/AMDGPU/SIInstructions.td
===================================================================
--- lib/Target/AMDGPU/SIInstructions.td
+++ lib/Target/AMDGPU/SIInstructions.td
@@ -1327,11 +1327,21 @@
   (S_XOR_B64 $src0, $src1)
 >;
 
+def : GCNPat <
+  (i1 (sub i1:$src0, i1:$src1)),
+  (S_XOR_B64 $src0, $src1)
+>;
+
 let AddedComplexity = 1 in {
 def : GCNPat <
   (i1 (add i1:$src0, (i1 -1))),
   (S_NOT_B64 $src0)
 >;
+
+def : GCNPat <
+  (i1 (sub i1:$src0, (i1 -1))),
+  (S_NOT_B64 $src0)
+>;
 }
 
 def : GCNPat <


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