[llvm] r343851 - [TargetRegisterInfo] Remove temporary hook enableMultipleCopyHints()
Jonas Paulsson via llvm-commits
llvm-commits at lists.llvm.org
Fri Oct 5 07:23:11 PDT 2018
Author: jonpa
Date: Fri Oct 5 07:23:11 2018
New Revision: 343851
URL: http://llvm.org/viewvc/llvm-project?rev=343851&view=rev
Log:
[TargetRegisterInfo] Remove temporary hook enableMultipleCopyHints()
Finally all targets are enabling multiple regalloc hints, so the hook to
disable this can now be removed.
NFC.
Review: Simon Pilgrim
https://reviews.llvm.org/D52316
Modified:
llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h
llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp
llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.h
llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterInfo.h
llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
llvm/trunk/lib/Target/BPF/BPFRegisterInfo.h
llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.h
llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h
llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h
llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h
llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h
llvm/trunk/lib/Target/X86/X86RegisterInfo.h
llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h
Modified: llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h?rev=343851&r1=343850&r2=343851&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/TargetRegisterInfo.h Fri Oct 5 07:23:11 2018
@@ -824,13 +824,6 @@ public:
// Do nothing.
}
- /// The creation of multiple copy hints have been implemented in
- /// weightCalcHelper(), but since this affects so many tests for many
- /// targets, this is temporarily disabled per default. THIS SHOULD BE
- /// "GENERAL GOODNESS" and hopefully all targets will update their tests
- /// and enable this soon. This hook should then be removed.
- virtual bool enableMultipleCopyHints() const { return false; }
-
/// Allow the target to reverse allocation order of local live ranges. This
/// will generally allocate shorter local live ranges first. For targets with
/// many registers, this could reduce regalloc compile time by a large
Modified: llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp?rev=343851&r1=343850&r2=343851&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp (original)
+++ llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp Fri Oct 5 07:23:11 2018
@@ -70,15 +70,6 @@ static unsigned copyHint(const MachineIn
return sub == hsub ? hreg : 0;
const TargetRegisterClass *rc = mri.getRegClass(reg);
- if (!tri.enableMultipleCopyHints()) {
- // Only allow physreg hints in rc.
- if (sub == 0)
- return rc->contains(hreg) ? hreg : 0;
-
- // reg:sub should match the physreg hreg.
- return tri.getMatchingSuperReg(hreg, sub, rc);
- }
-
unsigned CopiedPReg = (hsub ? tri.getSubReg(hreg, hsub) : hreg);
if (rc->contains(CopiedPReg))
return CopiedPReg;
@@ -199,31 +190,19 @@ float VirtRegAuxInfo::weightCalcHelper(L
unsigned Reg;
float Weight;
bool IsPhys;
- unsigned HintOrder;
- CopyHint(unsigned R, float W, bool P, unsigned HR) :
- Reg(R), Weight(W), IsPhys(P), HintOrder(HR) {}
+ CopyHint(unsigned R, float W, bool P) :
+ Reg(R), Weight(W), IsPhys(P) {}
bool operator<(const CopyHint &rhs) const {
// Always prefer any physreg hint.
if (IsPhys != rhs.IsPhys)
return (IsPhys && !rhs.IsPhys);
if (Weight != rhs.Weight)
return (Weight > rhs.Weight);
-
- // This is just a temporary way to achive NFC for targets that don't
- // enable multiple copy hints. HintOrder should be removed when all
- // targets return true in enableMultipleCopyHints().
- return (HintOrder < rhs.HintOrder);
-
-#if 0 // Should replace the HintOrder check, see above.
- // (just for the purpose of maintaining the set)
- return Reg < rhs.Reg;
-#endif
+ return Reg < rhs.Reg; // Tie-breaker.
}
};
std::set<CopyHint> CopyHints;
- // Temporary: see comment for HintOrder above.
- unsigned CopyHintOrder = 0;
for (MachineRegisterInfo::reg_instr_iterator
I = mri.reg_instr_begin(li.reg), E = mri.reg_instr_end();
I != E; ) {
@@ -263,8 +242,7 @@ float VirtRegAuxInfo::weightCalcHelper(L
}
// Get allocation hints from copies.
- if (!mi->isCopy() ||
- (TargetHint.first != 0 && !tri.enableMultipleCopyHints()))
+ if (!mi->isCopy())
continue;
unsigned hint = copyHint(mi, li.reg, tri, mri);
if (!hint)
@@ -275,8 +253,7 @@ float VirtRegAuxInfo::weightCalcHelper(L
// FIXME: we probably shouldn't use floats at all.
volatile float hweight = Hint[hint] += weight;
if (TargetRegisterInfo::isVirtualRegister(hint) || mri.isAllocatable(hint))
- CopyHints.insert(CopyHint(hint, hweight, tri.isPhysicalRegister(hint),
- (tri.enableMultipleCopyHints() ? hint : CopyHintOrder++)));
+ CopyHints.insert(CopyHint(hint, hweight, tri.isPhysicalRegister(hint)));
}
Hint.clear();
@@ -294,8 +271,6 @@ float VirtRegAuxInfo::weightCalcHelper(L
// Don't add the same reg twice or the target-type hint again.
continue;
mri.addRegAllocationHint(li.reg, Hint.Reg);
- if (!tri.enableMultipleCopyHints())
- break;
}
// Weakly boost the spill weight of hinted registers.
Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.h?rev=343851&r1=343850&r2=343851&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterInfo.h Fri Oct 5 07:23:11 2018
@@ -84,8 +84,6 @@ public:
const TargetRegisterClass *
getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
- bool enableMultipleCopyHints() const override { return true; }
-
bool requiresRegisterScavenging(const MachineFunction &MF) const override;
bool useFPForScavengingIndex(const MachineFunction &MF) const override;
bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
Modified: llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterInfo.h?rev=343851&r1=343850&r2=343851&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterInfo.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPURegisterInfo.h Fri Oct 5 07:23:11 2018
@@ -27,8 +27,6 @@ class TargetInstrInfo;
struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
AMDGPURegisterInfo();
- bool enableMultipleCopyHints() const override { return true; }
-
/// \returns the sub reg enum value for the given \p Channel
/// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)
static unsigned getSubRegFromChannel(unsigned Channel);
Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=343851&r1=343850&r2=343851&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Fri Oct 5 07:23:11 2018
@@ -156,7 +156,6 @@ public:
void updateRegAllocHint(unsigned Reg, unsigned NewReg,
MachineFunction &MF) const override;
- bool enableMultipleCopyHints() const override { return true; }
bool hasBasePointer(const MachineFunction &MF) const;
Modified: llvm/trunk/lib/Target/BPF/BPFRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/BPF/BPFRegisterInfo.h?rev=343851&r1=343850&r2=343851&view=diff
==============================================================================
--- llvm/trunk/lib/Target/BPF/BPFRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/BPF/BPFRegisterInfo.h Fri Oct 5 07:23:11 2018
@@ -29,8 +29,6 @@ struct BPFRegisterInfo : public BPFGenRe
BitVector getReservedRegs(const MachineFunction &MF) const override;
- bool enableMultipleCopyHints() const override { return true; }
-
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
unsigned FIOperandNum,
RegScavenger *RS = nullptr) const override;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.h?rev=343851&r1=343850&r2=343851&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonRegisterInfo.h Fri Oct 5 07:23:11 2018
@@ -39,8 +39,6 @@ public:
BitVector getReservedRegs(const MachineFunction &MF) const override;
- bool enableMultipleCopyHints() const override { return true; }
-
void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
unsigned FIOperandNum, RegScavenger *RS = nullptr) const override;
Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h?rev=343851&r1=343850&r2=343851&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h Fri Oct 5 07:23:11 2018
@@ -57,8 +57,6 @@ public:
BitVector getReservedRegs(const MachineFunction &MF) const override;
- bool enableMultipleCopyHints() const override { return true; }
-
bool requiresRegisterScavenging(const MachineFunction &MF) const override;
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h?rev=343851&r1=343850&r2=343851&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h Fri Oct 5 07:23:11 2018
@@ -85,8 +85,6 @@ public:
BitVector getReservedRegs(const MachineFunction &MF) const override;
bool isCallerPreservedPhysReg(unsigned PhysReg, const MachineFunction &MF) const override;
- bool enableMultipleCopyHints() const override { return true; }
-
/// We require the register scavenger.
bool requiresRegisterScavenging(const MachineFunction &MF) const override {
return true;
Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h?rev=343851&r1=343850&r2=343851&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h Fri Oct 5 07:23:11 2018
@@ -35,8 +35,6 @@ struct SparcRegisterInfo : public SparcG
const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
unsigned Kind) const override;
- bool enableMultipleCopyHints() const override { return true; }
-
void eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum,
RegScavenger *RS = nullptr) const override;
Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h?rev=343851&r1=343850&r2=343851&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h Fri Oct 5 07:23:11 2018
@@ -57,8 +57,6 @@ public:
const VirtRegMap *VRM,
const LiveRegMatrix *Matrix) const override;
- bool enableMultipleCopyHints() const override { return true; }
-
// Override TargetRegisterInfo.h.
bool requiresRegisterScavenging(const MachineFunction &MF) const override {
return true;
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.h?rev=343851&r1=343850&r2=343851&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.h Fri Oct 5 07:23:11 2018
@@ -95,8 +95,6 @@ public:
unsigned getRegPressureLimit(const TargetRegisterClass *RC,
MachineFunction &MF) const override;
- bool enableMultipleCopyHints() const override { return true; }
-
/// getCalleeSavedRegs - Return a null-terminated list of all of the
/// callee-save registers on this target.
const MCPhysReg *
Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h?rev=343851&r1=343850&r2=343851&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h Fri Oct 5 07:23:11 2018
@@ -33,8 +33,6 @@ public:
BitVector getReservedRegs(const MachineFunction &MF) const override;
- bool enableMultipleCopyHints() const override { return true; }
-
bool requiresRegisterScavenging(const MachineFunction &MF) const override;
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
More information about the llvm-commits
mailing list