[PATCH] D52886: [X86] Move ReadAfterLd functionality into X86FoldableSchedWrite (PR36957)

[Clement Courbet via Phabricator via llvm-commits]

courbet added inline comments.


================
Comment at: lib/Target/X86/X86SchedBroadwell.td:79
 
+// Vector loads are 5/5/6 cycles, so ReadAfterVec*Ld registers needn't be available
+// until 5/5/6 cycles after the memory operand.
----------------
courbet wrote:
> RKSimon wrote:
> > craig.topper wrote:
> > > The load latencies on BDW seem weird given that HSW and SKL, the CPUs immediately before and after are the same.
> > They're the same as BDW's load latencies - can we confirm if they are correct or not? I think this question has come up several times in the past....
> llvm-exegesis does not currently fully automate measurement of latency operations, nevertheless we can do:
> 
> ```
> echo -e 'mov (%rdi),%rax\n mov %rax, 1(%rdi)' | ./bin/llvm-exegesis -mode=latency -snippets-file=-
> echo -e 'vmovups (%rdi),%xmm0\n vmovups %xmm0, 1(%rdi)' | ./bin/llvm-exegesis -mode=latency -snippets-file=-
> echo -e 'vmovups (%rdi),%ymm0\n vmovups %ymm0, 1(%rdi)' | ./bin/llvm-exegesis -mode=latency -snippets-file=-
> ```
> (with store-to-load forwarding)
> 
> ```
> echo -e 'mov (%rdi),%rax\n mov %rax, 1(%rdi)' | ./bin/llvm-exegesis -mode=latency -snippets-file=-
> echo -e 'vmovups (%rdi),%xmm0\n vmovups %xmm0, 1(%rdi)' | ./bin/llvm-exegesis -mode=latency -snippets-file=-
> echo -e 'vmovups (%rdi),%ymm0\n vmovups %ymm0, 1(%rdi)' | ./bin/llvm-exegesis -mode=latency -snippets-file=-
> ```
> (without store-to-load forwarding)
> 
> On Haswell, this gives 5/6/7-15/16/17.
> On Broadwell, this gives 5/6/7-15/16/17.
> 
> So they should be the same (5/6/7).
> 
> 
> `echo -e 'mov (%rdi),%rax\n mov %rax, 1(%rdi)' | ./bin/llvm-exegesis -mode=latency -snippets-file=-`

This was supposed to be:
`echo -e 'mov (%rdi),%rax\n mov %rax, (%rdi)' | ./bin/llvm-exegesis -mode=latency -snippets-file=-`



Repository:
  rL LLVM

https://reviews.llvm.org/D52886