[PATCH] D52846: [AMDGPU] Add FixupVectorISel pass, currently Supports SREGs in GLOBAL LD/ST
Ron Lieberman via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 3 13:58:10 PDT 2018
ronlieb created this revision.
ronlieb added reviewers: AMDGPU, arsenm, rampitec.
Herald added subscribers: jfb, t-tye, tpr, dstuttard, yaxunl, mgorny, nhaehnle, wdng, jvesely, kzhuravl.
Add a pass to fixup various vector ISel issues.
Currently we handle converting GLOBAL_{LOAD|STORE}_*
and GLOBAL_Atomic_* instructions into their _SADDR variants.
This involves feeding the sreg into the saddr field of the new instruction.
https://reviews.llvm.org/D52846
Files:
lib/Target/AMDGPU/AMDGPU.h
lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
lib/Target/AMDGPU/CMakeLists.txt
lib/Target/AMDGPU/FLATInstructions.td
lib/Target/AMDGPU/SIFixupVectorISel.cpp
lib/Target/AMDGPU/SIInstrInfo.h
lib/Target/AMDGPU/SIInstrInfo.td
test/CodeGen/AMDGPU/cgp-addressing-modes.ll
test/CodeGen/AMDGPU/conv2d-saddr.ll
test/CodeGen/AMDGPU/ds_write2.ll
test/CodeGen/AMDGPU/ds_write2st64.ll
test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
test/CodeGen/AMDGPU/insert_vector_elt.v2i16.subtest-nosaddr.ll
test/CodeGen/AMDGPU/insert_vector_elt.v2i16.subtest-saddr.ll
test/CodeGen/AMDGPU/madak.ll
test/CodeGen/AMDGPU/memory-legalizer-load.ll
test/CodeGen/AMDGPU/memory-legalizer-store.ll
test/CodeGen/AMDGPU/memory_clause.ll
test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D52846.168164.patch
Type: text/x-patch
Size: 45675 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20181003/af45d580/attachment.bin>
More information about the llvm-commits
mailing list