[llvm] r343741 - [RISCV] Handle redundant SplitF64+BuildPairF64 pairs in a DAGCombine

[Alex Bradbury via llvm-commits]

Author: asb
Date: Wed Oct  3 16:30:16 2018
New Revision: 343741

URL: http://llvm.org/viewvc/llvm-project?rev=343741&view=rev
Log:
[RISCV] Handle redundant SplitF64+BuildPairF64 pairs in a DAGCombine

r343712 performed this optimisation during instruction selection. As Eli 
Friedman pointed out in post-commit review, implementing this as a DAGCombine 
might allow opportunities for further optimisations.

Modified:
    llvm/trunk/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h

Modified: llvm/trunk/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVISelDAGToDAG.cpp?rev=343741&r1=343740&r2=343741&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVISelDAGToDAG.cpp Wed Oct  3 16:30:16 2018
@@ -96,18 +96,6 @@ void RISCVDAGToDAGISel::Select(SDNode *N
     ReplaceNode(Node, CurDAG->getMachineNode(RISCV::ADDI, DL, VT, TFI, Imm));
     return;
   }
-  case RISCVISD::SplitF64: {
-    // If the input to SplitF64 is just BuildPairF64 then the operation is
-    // redundant. Instead, use BuildPairF64's operands directly. This pattern
-    // can't be written in tablegen due to the multiple outputs.
-    SDValue Op0 = Node->getOperand(0);
-    if (Op0->getOpcode() != RISCVISD::BuildPairF64)
-      break;
-    ReplaceUses(SDValue(Node, 0), Op0.getOperand(0));
-    ReplaceUses(SDValue(Node, 1), Op0.getOperand(1));
-    CurDAG->RemoveDeadNode(Node);
-    return;
-  }
   }
 
   // Select the default instruction.

Modified: llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp?rev=343741&r1=343740&r2=343741&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp Wed Oct  3 16:30:16 2018
@@ -494,6 +494,24 @@ SDValue RISCVTargetLowering::LowerRETURN
   return DAG.getCopyFromReg(DAG.getEntryNode(), DL, Reg, XLenVT);
 }
 
+SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
+                                               DAGCombinerInfo &DCI) const {
+  switch (N->getOpcode()) {
+  default:
+    break;
+  case RISCVISD::SplitF64: {
+    // If the input to SplitF64 is just BuildPairF64 then the operation is
+    // redundant. Instead, use BuildPairF64's operands directly.
+    SDValue Op0 = N->getOperand(0);
+    if (Op0->getOpcode() != RISCVISD::BuildPairF64)
+      break;
+    return DCI.CombineTo(N, Op0.getOperand(0), Op0.getOperand(1));
+  }
+  }
+
+  return SDValue();
+}
+
 static MachineBasicBlock *emitSplitF64Pseudo(MachineInstr &MI,
                                              MachineBasicBlock *BB) {
   assert(MI.getOpcode() == RISCV::SplitF64Pseudo && "Unexpected instruction");

Modified: llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h?rev=343741&r1=343740&r2=343741&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVISelLowering.h Wed Oct  3 16:30:16 2018
@@ -58,6 +58,8 @@ public:
   // Provide custom lowering hooks for some operations.
   SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
 
+  SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
+
   // This method returns the name of a target specific DAG node.
   const char *getTargetNodeName(unsigned Opcode) const override;