[llvm] r343712 - [RISCV][NFCI] Handle redundant splitf64+buildpairf64 pairs during instruction selection

[Friedman, Eli via llvm-commits]

On 10/3/2018 1:12 PM, Alex Bradbury via llvm-commits wrote:
> Author: asb
> Date: Wed Oct  3 13:12:10 2018
> New Revision: 343712
>
> URL: http://llvm.org/viewvc/llvm-project?rev=343712&view=rev
> Log:
> [RISCV][NFCI] Handle redundant splitf64+buildpairf64 pairs during instruction selection
>
> Although we can't write a tablegen pattern to remove redundant
> splitf64+buildf64 pairs due to the multiple return values, we can handle it
> with some C++ selection code. This is simpler than removing them after
> instruction selection through RISCVDAGToDAGISel::PostprocessISelDAG, as was
> done previously.

Could you write this as a DAGCombine instead?  Might allow other 
optimizations.

-Eli

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