[PATCH] D52833: [RISCV] Add codegen test for RV64 ALU operations

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added a comment.

rv64i has a few specific `*w` instructions that we probably want to test them too. For instance,

  define signext i32 @addiw(i32 signext %a) {
  ; RV64I-LABEL: addiw:
  ; RV64I:       # %bb.0:
  ; RV64I-NEXT:    addiw a0, a0, 123
  ; RV64I-NEXT:    ret
    %1 = add i32 %a, 123
    ret i32 %1
  }

Not sure if we want to make this file i64 only and use another one (e.g. `alu64-i32.ll`) for the `*w` instructions.


Repository:
  rL LLVM

https://reviews.llvm.org/D52833