[llvm] r343678 - [RISCV] Remove XLenVT==i32 assumptions from RISCVInstrInfo td
Alex Bradbury via llvm-commits
llvm-commits at lists.llvm.org
Wed Oct 3 04:14:26 PDT 2018
Author: asb
Date: Wed Oct 3 04:14:26 2018
New Revision: 343678
URL: http://llvm.org/viewvc/llvm-project?rev=343678&view=rev
Log:
[RISCV] Remove XLenVT==i32 assumptions from RISCVInstrInfo td
1. brcond operates on an condition.
2. atomic_fence and the pseudo AMO instructions should all take xlen immediates
This allows the same definitions and patterns to work for RV64 (XLenVT==i64).
Modified:
llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
llvm/trunk/lib/Target/RISCV/RISCVInstrInfoA.td
Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td?rev=343678&r1=343677&r2=343678&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfo.td Wed Oct 3 04:14:26 2018
@@ -686,7 +686,7 @@ def Select_GPR_Using_CC_GPR : SelectCC_r
// Match `(brcond (CondOp ..), ..)` and lower to the appropriate RISC-V branch
// instruction.
class BccPat<PatFrag CondOp, RVInstB Inst>
- : Pat<(brcond (i32 (CondOp GPR:$rs1, GPR:$rs2)), bb:$imm12),
+ : Pat<(brcond (XLenVT (CondOp GPR:$rs1, GPR:$rs2)), bb:$imm12),
(Inst GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12)>;
def : BccPat<seteq, BEQ>;
@@ -697,7 +697,7 @@ def : BccPat<setult, BLTU>;
def : BccPat<setuge, BGEU>;
class BccSwapPat<PatFrag CondOp, RVInst InstBcc>
- : Pat<(brcond (i32 (CondOp GPR:$rs1, GPR:$rs2)), bb:$imm12),
+ : Pat<(brcond (XLenVT (CondOp GPR:$rs1, GPR:$rs2)), bb:$imm12),
(InstBcc GPR:$rs2, GPR:$rs1, bb:$imm12)>;
// Condition codes that don't have matching RISC-V branch instructions, but
@@ -817,13 +817,13 @@ defm : StPat<store, SW, GPR>, Requires<[
// Manual: Volume I.
// fence acquire -> fence r, rw
-def : Pat<(atomic_fence (i32 4), (imm)), (FENCE 0b10, 0b11)>;
+def : Pat<(atomic_fence (XLenVT 4), (imm)), (FENCE 0b10, 0b11)>;
// fence release -> fence rw, w
-def : Pat<(atomic_fence (i32 5), (imm)), (FENCE 0b11, 0b1)>;
+def : Pat<(atomic_fence (XLenVT 5), (imm)), (FENCE 0b11, 0b1)>;
// fence acq_rel -> fence.tso
-def : Pat<(atomic_fence (i32 6), (imm)), (FENCE_TSO)>;
+def : Pat<(atomic_fence (XLenVT 6), (imm)), (FENCE_TSO)>;
// fence seq_cst -> fence rw, rw
-def : Pat<(atomic_fence (i32 7), (imm)), (FENCE 0b11, 0b11)>;
+def : Pat<(atomic_fence (XLenVT 7), (imm)), (FENCE 0b11, 0b11)>;
// Lowering for atomic load and store is defined in RISCVInstrInfoA.td.
// Although these are lowered to fence+load/store instructions defined in the
Modified: llvm/trunk/lib/Target/RISCV/RISCVInstrInfoA.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVInstrInfoA.td?rev=343678&r1=343677&r2=343678&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVInstrInfoA.td (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVInstrInfoA.td Wed Oct 3 04:14:26 2018
@@ -145,7 +145,7 @@ def : Pat<(atomic_load_sub_32_seq_cst GP
/// Pseudo AMOs
class PseudoAMO : Pseudo<(outs GPR:$res, GPR:$scratch),
- (ins GPR:$addr, GPR:$incr, i32imm:$ordering), []> {
+ (ins GPR:$addr, GPR:$incr, ixlenimm:$ordering), []> {
let Constraints = "@earlyclobber $res, at earlyclobber $scratch";
let mayLoad = 1;
let mayStore = 1;
@@ -168,7 +168,7 @@ def : Pat<(atomic_load_nand_32_seq_cst G
class PseudoMaskedAMO
: Pseudo<(outs GPR:$res, GPR:$scratch),
- (ins GPR:$addr, GPR:$incr, GPR:$mask, i32imm:$ordering), []> {
+ (ins GPR:$addr, GPR:$incr, GPR:$mask, ixlenimm:$ordering), []> {
let Constraints = "@earlyclobber $res, at earlyclobber $scratch";
let mayLoad = 1;
let mayStore = 1;
@@ -177,8 +177,8 @@ class PseudoMaskedAMO
class PseudoMaskedAMOMinMax
: Pseudo<(outs GPR:$res, GPR:$scratch1, GPR:$scratch2),
- (ins GPR:$addr, GPR:$incr, GPR:$mask, i32imm:$sextshamt,
- i32imm:$ordering), []> {
+ (ins GPR:$addr, GPR:$incr, GPR:$mask, ixlenimm:$sextshamt,
+ ixlenimm:$ordering), []> {
let Constraints = "@earlyclobber $res, at earlyclobber $scratch1,"
"@earlyclobber $scratch2";
let mayLoad = 1;
@@ -188,7 +188,7 @@ class PseudoMaskedAMOMinMax
class PseudoMaskedAMOUMinUMax
: Pseudo<(outs GPR:$res, GPR:$scratch1, GPR:$scratch2),
- (ins GPR:$addr, GPR:$incr, GPR:$mask, i32imm:$ordering), []> {
+ (ins GPR:$addr, GPR:$incr, GPR:$mask, ixlenimm:$ordering), []> {
let Constraints = "@earlyclobber $res, at earlyclobber $scratch1,"
"@earlyclobber $scratch2";
let mayLoad = 1;
More information about the llvm-commits
mailing list