[PATCH] D52116: Introduce llvm.loop.parallel_accesses and llvm.access.group metadata.

[Pekka Jääskeläinen via Phabricator via llvm-commits]

pekka.jaaskelainen accepted this revision.
pekka.jaaskelainen added a comment.
This revision is now accepted and ready to land.

Thanks for making this MD more robust! It is essential for the vectorization performance of pocl. Sorry for my slow response time.

Related to OpenCL, there's usually a 3D work-item loop all of which levels are parallel. I didn't spot a test that shows multiple loop levels and thus multiple parallel access groups attached to an instruction. Moreover, the inliner MD transfer would indeed be much improved in case it then replicated the parallel access info from all loop hierarchy levels downwards. The comment which mentions that you focus on inner loop is true, but if there is (or will be) a loop interchange optimization pass that utilizes the parallel loop info, then any loop level might be potentially transferred to be the inner loop.

This is again very useful for OpenCL work-item loops as it allows optimizing memory access patterns via loop interchange, thus essentially performing outer loop vectorization when it's the best way to get performance.


Repository:
  rL LLVM

https://reviews.llvm.org/D52116