[PATCH] D52769: [AMDGPU] Assert in getOpSize() there are no sub-dword subregs

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL343648: [AMDGPU] Assert in getOpSize() there are no sub-dword subregs (authored by rampitec, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D52769?vs=167883&id=168056#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D52769

Files:
  llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h


Index: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h
@@ -732,8 +732,13 @@
   unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
     const MachineOperand &MO = MI.getOperand(OpNo);
     if (MO.isReg()) {
-      if (unsigned SubReg = MO.getSubReg())
+      if (unsigned SubReg = MO.getSubReg()) {
+        assert(RI.getRegSizeInBits(*RI.getSubClassWithSubReg(
+                                   MI.getParent()->getParent()->getRegInfo().
+                                     getRegClass(MO.getReg()), SubReg)) >= 32 &&
+               "Sub-dword subregs are not supported");
         return RI.getSubRegIndexLaneMask(SubReg).getNumLanes() * 4;
+      }
     }
     return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
   }


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