[PATCH] D52817: AMDGPU: Only add implicit super-reg def for first subreg
Matt Arsenault via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 2 18:24:04 PDT 2018
arsenm created this revision.
arsenm added reviewers: rampitec, MatzeB.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.
https://reviews.llvm.org/D52817
Files:
lib/Target/AMDGPU/SIRegisterInfo.cpp
Index: lib/Target/AMDGPU/SIRegisterInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -901,7 +901,7 @@
.addImm(0) // glc
.addMemOperand(MMO);
- if (NumSubRegs > 1)
+ if (NumSubRegs > 1 && i == 0)
MIB.addReg(SuperReg, RegState::ImplicitDefine);
continue;
@@ -915,7 +915,7 @@
.addReg(Spill.VGPR)
.addImm(Spill.Lane);
- if (NumSubRegs > 1)
+ if (NumSubRegs > 1 && i == 0)
MIB.addReg(SuperReg, RegState::ImplicitDefine);
} else {
if (OnlyToVGPR)
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