[llvm] r343648 - [AMDGPU] Assert in getOpSize() there are no sub-dword subregs

[Stanislav Mekhanoshin via llvm-commits]

Author: rampitec
Date: Tue Oct  2 17:00:41 2018
New Revision: 343648

URL: http://llvm.org/viewvc/llvm-project?rev=343648&view=rev
Log:
[AMDGPU] Assert in getOpSize() there are no sub-dword subregs

Differential Revision: https://reviews.llvm.org/D52769

Modified:
    llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h

Modified: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h?rev=343648&r1=343647&r2=343648&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h (original)
+++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h Tue Oct  2 17:00:41 2018
@@ -732,8 +732,13 @@ public:
   unsigned getOpSize(const MachineInstr &MI, unsigned OpNo) const {
     const MachineOperand &MO = MI.getOperand(OpNo);
     if (MO.isReg()) {
-      if (unsigned SubReg = MO.getSubReg())
+      if (unsigned SubReg = MO.getSubReg()) {
+        assert(RI.getRegSizeInBits(*RI.getSubClassWithSubReg(
+                                   MI.getParent()->getParent()->getRegInfo().
+                                     getRegClass(MO.getReg()), SubReg)) >= 32 &&
+               "Sub-dword subregs are not supported");
         return RI.getSubRegIndexLaneMask(SubReg).getNumLanes() * 4;
+      }
     }
     return RI.getRegSizeInBits(*getOpRegClass(MI, OpNo)) / 8;
   }