[llvm] r343616 - Revert "X86, AArch64, ARM: Do not attach debug location to spill/reload instructions"
Matt Morehouse via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 2 11:35:44 PDT 2018
Author: morehouse
Date: Tue Oct 2 11:35:44 2018
New Revision: 343616
URL: http://llvm.org/viewvc/llvm-project?rev=343616&view=rev
Log:
Revert "X86, AArch64, ARM: Do not attach debug location to spill/reload instructions"
This reverts r343520 due to breakage of HWASan tests on Android.
Removed:
llvm/trunk/test/CodeGen/AArch64/spill-debuginfo.mir
Modified:
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
llvm/trunk/test/DebugInfo/X86/fission-ranges.ll
llvm/trunk/test/DebugInfo/X86/parameters.ll
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp?rev=343616&r1=343615&r2=343616&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp Tue Oct 2 11:35:44 2018
@@ -2748,6 +2748,9 @@ void AArch64InstrInfo::storeRegToStackSl
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg,
bool isKill, int FI, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
+ DebugLoc DL;
+ if (MBBI != MBB.end())
+ DL = MBBI->getDebugLoc();
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo();
unsigned Align = MFI.getObjectAlignment(FI);
@@ -2794,7 +2797,7 @@ void AArch64InstrInfo::storeRegToStackSl
Opc = AArch64::ST1Twov1d;
Offset = false;
} else if (AArch64::XSeqPairsClassRegClass.hasSubClassEq(RC)) {
- BuildMI(MBB, MBBI, DebugLoc(), get(AArch64::STPXi))
+ BuildMI(MBB, MBBI, DL, get(AArch64::STPXi))
.addReg(TRI->getSubReg(SrcReg, AArch64::sube64),
getKillRegState(isKill))
.addReg(TRI->getSubReg(SrcReg, AArch64::subo64),
@@ -2840,7 +2843,7 @@ void AArch64InstrInfo::storeRegToStackSl
}
assert(Opc && "Unknown register class");
- const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DebugLoc(), get(Opc))
+ const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DL, get(Opc))
.addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI);
@@ -2853,6 +2856,9 @@ void AArch64InstrInfo::loadRegFromStackS
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg,
int FI, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
+ DebugLoc DL;
+ if (MBBI != MBB.end())
+ DL = MBBI->getDebugLoc();
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo();
unsigned Align = MFI.getObjectAlignment(FI);
@@ -2899,7 +2905,7 @@ void AArch64InstrInfo::loadRegFromStackS
Opc = AArch64::LD1Twov1d;
Offset = false;
} else if (AArch64::XSeqPairsClassRegClass.hasSubClassEq(RC)) {
- BuildMI(MBB, MBBI, DebugLoc(), get(AArch64::LDPXi))
+ BuildMI(MBB, MBBI, DL, get(AArch64::LDPXi))
.addReg(TRI->getSubReg(DestReg, AArch64::sube64),
getDefRegState(true))
.addReg(TRI->getSubReg(DestReg, AArch64::subo64),
@@ -2945,7 +2951,7 @@ void AArch64InstrInfo::loadRegFromStackS
}
assert(Opc && "Unknown register class");
- const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DebugLoc(), get(Opc))
+ const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DL, get(Opc))
.addReg(DestReg, getDefRegState(true))
.addFrameIndex(FI);
if (Offset)
Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=343616&r1=343615&r2=343616&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Oct 2 11:35:44 2018
@@ -971,6 +971,8 @@ storeRegToStackSlot(MachineBasicBlock &M
unsigned SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const {
+ DebugLoc DL;
+ if (I != MBB.end()) DL = I->getDebugLoc();
MachineFunction &MF = *MBB.getParent();
MachineFrameInfo &MFI = MF.getFrameInfo();
unsigned Align = MFI.getObjectAlignment(FI);
@@ -982,7 +984,7 @@ storeRegToStackSlot(MachineBasicBlock &M
switch (TRI->getSpillSize(*RC)) {
case 2:
if (ARM::HPRRegClass.hasSubClassEq(RC)) {
- BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRH))
+ BuildMI(MBB, I, DL, get(ARM::VSTRH))
.addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI)
.addImm(0)
@@ -993,14 +995,14 @@ storeRegToStackSlot(MachineBasicBlock &M
break;
case 4:
if (ARM::GPRRegClass.hasSubClassEq(RC)) {
- BuildMI(MBB, I, DebugLoc(), get(ARM::STRi12))
+ BuildMI(MBB, I, DL, get(ARM::STRi12))
.addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI)
.addImm(0)
.addMemOperand(MMO)
.add(predOps(ARMCC::AL));
} else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
- BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRS))
+ BuildMI(MBB, I, DL, get(ARM::VSTRS))
.addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI)
.addImm(0)
@@ -1011,7 +1013,7 @@ storeRegToStackSlot(MachineBasicBlock &M
break;
case 8:
if (ARM::DPRRegClass.hasSubClassEq(RC)) {
- BuildMI(MBB, I, DebugLoc(), get(ARM::VSTRD))
+ BuildMI(MBB, I, DL, get(ARM::VSTRD))
.addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI)
.addImm(0)
@@ -1019,7 +1021,7 @@ storeRegToStackSlot(MachineBasicBlock &M
.add(predOps(ARMCC::AL));
} else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
if (Subtarget.hasV5TEOps()) {
- MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STRD));
+ MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
@@ -1027,7 +1029,7 @@ storeRegToStackSlot(MachineBasicBlock &M
} else {
// Fallback to STM instruction, which has existed since the dawn of
// time.
- MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STMIA))
+ MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STMIA))
.addFrameIndex(FI)
.addMemOperand(MMO)
.add(predOps(ARMCC::AL));
@@ -1041,14 +1043,14 @@ storeRegToStackSlot(MachineBasicBlock &M
if (ARM::DPairRegClass.hasSubClassEq(RC)) {
// Use aligned spills if the stack can be realigned.
if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
- BuildMI(MBB, I, DebugLoc(), get(ARM::VST1q64))
+ BuildMI(MBB, I, DL, get(ARM::VST1q64))
.addFrameIndex(FI)
.addImm(16)
.addReg(SrcReg, getKillRegState(isKill))
.addMemOperand(MMO)
.add(predOps(ARMCC::AL));
} else {
- BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMQIA))
+ BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
.addReg(SrcReg, getKillRegState(isKill))
.addFrameIndex(FI)
.addMemOperand(MMO)
@@ -1061,15 +1063,14 @@ storeRegToStackSlot(MachineBasicBlock &M
if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
// Use aligned spills if the stack can be realigned.
if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
- BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64TPseudo))
+ BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
.addFrameIndex(FI)
.addImm(16)
.addReg(SrcReg, getKillRegState(isKill))
.addMemOperand(MMO)
.add(predOps(ARMCC::AL));
} else {
- MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(),
- get(ARM::VSTMDIA))
+ MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
.addFrameIndex(FI)
.add(predOps(ARMCC::AL))
.addMemOperand(MMO);
@@ -1085,15 +1086,14 @@ storeRegToStackSlot(MachineBasicBlock &M
if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
// FIXME: It's possible to only store part of the QQ register if the
// spilled def has a sub-register index.
- BuildMI(MBB, I, DebugLoc(), get(ARM::VST1d64QPseudo))
+ BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
.addFrameIndex(FI)
.addImm(16)
.addReg(SrcReg, getKillRegState(isKill))
.addMemOperand(MMO)
.add(predOps(ARMCC::AL));
} else {
- MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(),
- get(ARM::VSTMDIA))
+ MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
.addFrameIndex(FI)
.add(predOps(ARMCC::AL))
.addMemOperand(MMO);
@@ -1107,7 +1107,7 @@ storeRegToStackSlot(MachineBasicBlock &M
break;
case 64:
if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
- MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMDIA))
+ MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
.addFrameIndex(FI)
.add(predOps(ARMCC::AL))
.addMemOperand(MMO);
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=343616&r1=343615&r2=343616&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Oct 2 11:35:44 2018
@@ -3313,7 +3313,8 @@ void X86InstrInfo::storeRegToStackSlot(M
(Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
RI.canRealignStack(MF);
unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
- addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc)), FrameIdx)
+ DebugLoc DL = MBB.findDebugLoc(MI);
+ addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
.addReg(SrcReg, getKillRegState(isKill));
}
@@ -3347,7 +3348,8 @@ void X86InstrInfo::loadRegFromStackSlot(
(Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
RI.canRealignStack(MF);
unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
- addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg), FrameIdx);
+ DebugLoc DL = MBB.findDebugLoc(MI);
+ addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
}
void X86InstrInfo::loadRegFromAddr(
Removed: llvm/trunk/test/CodeGen/AArch64/spill-debuginfo.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/spill-debuginfo.mir?rev=343615&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/spill-debuginfo.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/spill-debuginfo.mir (removed)
@@ -1,32 +0,0 @@
-# RUN: llc -o - %s -run-pass=regallocfast | FileCheck %s
---- |
- target triple = "aarch64--"
-
- !0 = !DIFile(filename: "test.ll", directory: "/")
- !1 = distinct !DICompileUnit(file: !0, language: DW_LANG_C)
- !2 = distinct !DISubprogram(name: "test")
- !3 = !DILocation(line: 17, scope: !2)
- !4 = !DILocation(line: 42, scope: !2)
-
- define void @func() {
- unreachable
- }
-...
----
-# CHECK-LABEL: name: func
-name: func
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $x0
- ; CHECK: LDRXui killed $x0
- ; Should find a spill here, but it should not have a debug-location.
- ; CHECK-NOT: STRXui {{.*}}debug-location
- ; CHECK: BLR
- ; Should find a reload here, but it should not have a debug-location.
- ; CHECK-NOT: LDRXui {{.*}}debug-location
- ; CHECK: STRXui {{.*}}, killed $x0
- %0 : gpr64 = LDRXui $x0, 0, debug-location !3
- ; an instruction with regmask should force us to spill %0
- BLR undef $x0, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $x0, debug-location !3
- STRXui %0, $x0, 0, debug-location !4
Modified: llvm/trunk/test/DebugInfo/X86/fission-ranges.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/fission-ranges.ll?rev=343616&r1=343615&r2=343616&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/X86/fission-ranges.ll (original)
+++ llvm/trunk/test/DebugInfo/X86/fission-ranges.ll Tue Oct 2 11:35:44 2018
@@ -55,7 +55,7 @@
; V5RNGLISTS-NOT: DW_TAG
; V5RNGLISTS: DW_AT_rnglists_base [DW_FORM_sec_offset] (0x0000000c)
; V5RNGLISTS: .debug_rnglists contents:
-; V5RNGLISTS-NEXT: 0x00000000: range list header: length = 0x00000015, version = 0x0005,
+; V5RNGLISTS-NEXT: 0x00000000: range list header: length = 0x00000014, version = 0x0005,
; V5RNGLISTS-SAME: addr_size = 0x08, seg_size = 0x00, offset_entry_count = 0x00000000
; V5RNGLISTS-NEXT: ranges:
; V5RNGLISTS-NEXT: 0x0000000c: [DW_RLE_offset_pair]:
Modified: llvm/trunk/test/DebugInfo/X86/parameters.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/X86/parameters.ll?rev=343616&r1=343615&r2=343616&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/X86/parameters.ll (original)
+++ llvm/trunk/test/DebugInfo/X86/parameters.ll Tue Oct 2 11:35:44 2018
@@ -28,8 +28,7 @@
; CHECK: DW_TAG_subprogram
; CHECK: DW_AT_name{{.*}} = "func"
; CHECK: DW_TAG_formal_parameter
-; CHECK: DW_AT_location {{.*}}
-; CHECK-NEXT: DW_OP_breg4 RSI+0, DW_OP_deref
+; CHECK: DW_AT_location {{.*}} (DW_OP_breg4 RSI+0, DW_OP_deref)
; CHECK-NOT: DW_TAG
; CHECK: DW_AT_name{{.*}} = "f"
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