[PATCH] D50222: [CodeGen] [SelectionDAG] More efficient code for X % C == 0 (UREM case)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: test/CodeGen/AArch64/urem-seteq-vec-nonsplat.ll:6
 
-define <4 x i32> @test_urem_odd_div_nonsplat(<4 x i32> %X) nounwind readnone {
-; CHECK-LABEL: test_urem_odd_div_nonsplat:
+define <4 x i32> @test_urem_odd_div(<4 x i32> %X) nounwind readnone {
+; CHECK-LABEL: test_urem_odd_div:
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You can commit the nonsplat test name changes as an NFC now to reduce this patch.


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Comment at: test/CodeGen/X86/jump_sign.ll:405
+; CHECK-NEXT:    andl %ecx, %eax
+; CHECK-NEXT:    movb $-85, %dl
+; CHECK-NEXT:    # kill: def $al killed $al killed $eax
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hermord wrote:
> This is the `test1` regression I mentioned in previous updates. I've made it explicit now, for the lack of a clean fix that I can see (without `computeKnownBits`).
Have you made any progress working out what the problems is with test1?


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Comment at: test/CodeGen/X86/urem-seteq-vec-nonsplat.ll:10
 
-define <4 x i32> @test_urem_odd_div_nonsplat(<4 x i32> %X) nounwind readnone {
-; CHECK-SSE2-LABEL: test_urem_odd_div_nonsplat:
+define <4 x i32> @test_urem_odd_div(<4 x i32> %X) nounwind readnone {
+; CHECK-SSE2-LABEL: test_urem_odd_div:
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You can commit the nonsplat test name changes as an NFC now to reduce this patch.


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Comment at: test/CodeGen/X86/urem-seteq-vec-splat.ll:66
+; Like test_urem_odd_vec_i32, but with 8 x i16 vectors.
+define <8 x i16> @test_urem_odd_vec_i16(<8 x i16> %X) nounwind readnone {
 ; CHECK-SSE2-LABEL: test_urem_odd_vec_i16:
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These <4 x i16> -> <8 x i16> test changes need to be done as an NFC commit, showing the current codegen and then this patch rebased. Its up to you if you keep the aarch64 using <4 x i16> or not but the x86 versions need to be changed to a legal type.


Repository:
  rL LLVM

https://reviews.llvm.org/D50222