[llvm] r343596 - [Hexagon] Fix extracting subvectors of non-HVX vNi1

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Tue Oct  2 08:05:43 2018
New Revision: 343596

URL: http://llvm.org/viewvc/llvm-project?rev=343596&view=rev
Log:
[Hexagon] Fix extracting subvectors of non-HVX vNi1

Patch by Brendon Cahoon.

Added:
    llvm/trunk/test/CodeGen/Hexagon/vect/extract-v4i1.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp

Modified: llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp?rev=343596&r1=343595&r2=343596&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonISelLowering.cpp Tue Oct  2 08:05:43 2018
@@ -2362,8 +2362,9 @@ HexagonTargetLowering::extractVector(SDV
     // Generate (p2d VecV) >> 8*Idx to move the interesting bytes to
     // position 0.
     assert(ty(IdxV) == MVT::i32);
+    unsigned VecRep = 8 / VecWidth;
     SDValue S0 = DAG.getNode(ISD::MUL, dl, MVT::i32, IdxV,
-                             DAG.getConstant(8*Scale, dl, MVT::i32));
+                             DAG.getConstant(8*VecRep, dl, MVT::i32));
     SDValue T0 = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, VecV);
     SDValue T1 = DAG.getNode(ISD::SRL, dl, MVT::i64, T0, S0);
     while (Scale > 1) {

Added: llvm/trunk/test/CodeGen/Hexagon/vect/extract-v4i1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/vect/extract-v4i1.ll?rev=343596&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/vect/extract-v4i1.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/vect/extract-v4i1.ll Tue Oct  2 08:05:43 2018
@@ -0,0 +1,28 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; Test that the compiler generates the correct code when sign-extending a
+; predicate register when it is converted from one vector predicate type
+; to another. In this case, the compiler generates two v4i1 EXTRACT_SUBVECT
+; from a v8i1, for the lower and upper parts.
+
+; CHECK: r[[REGH:([0-9]+)]]:[[REGL:([0-9]+)]] = mask(p{{[0-3]}})
+; CHECK-DAG: = vsxtbh(r[[REGH]])
+; CHECK-DAG: = vsxtbh(r[[REGL]])
+
+target triple = "hexagon"
+
+define void @f0(i16* %a0, <8 x i16>* %a1) #0 {
+b0:
+  %v0 = load i16, i16* %a0, align 2
+  %v1 = sext i16 %v0 to i32
+  %v2 = insertelement <8 x i32> undef, i32 %v1, i32 0
+  %v3 = shufflevector <8 x i32> %v2, <8 x i32> undef, <8 x i32> zeroinitializer
+  %v4 = shl <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>, <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %v5 = and <8 x i32> %v4, %v3
+  %v6 = icmp ne <8 x i32> %v5, zeroinitializer
+  %v7 = zext <8 x i1> %v6 to <8 x i16>
+  store <8 x i16> %v7, <8 x i16>* %a1, align 8
+  ret void
+}
+
+attributes #0 = { nounwind optsize "target-cpu"="hexagonv65" "target-features"="+hvx-length64b,+hvxv65,-long-calls" }