[llvm] r343572 - [AArch64][v8.5A] Add Memory Tagging instructions
Oliver Stannard via llvm-commits
llvm-commits at lists.llvm.org
Tue Oct 2 03:04:39 PDT 2018
Author: olista01
Date: Tue Oct 2 03:04:39 2018
New Revision: 343572
URL: http://llvm.org/viewvc/llvm-project?rev=343572&view=rev
Log:
[AArch64][v8.5A] Add Memory Tagging instructions
This adds new instructions to manipluate tagged pointers, and to load
and store the tags associated with memory.
Patch by Pablo Barrio, David Spickett and Oliver Stannard!
Differential revision: https://reviews.llvm.org/D52490
Added:
llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-mte-unpredictable.txt
Modified:
llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
llvm/trunk/test/MC/AArch64/armv8.5a-mte-error.s
llvm/trunk/test/MC/AArch64/armv8.5a-mte.s
llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=343572&r1=343571&r2=343572&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td Tue Oct 2 03:04:39 2018
@@ -271,6 +271,12 @@ def simm10Scaled : Operand<i64> {
let PrintMethod = "printImmScale<8>";
}
+def simm9s16 : Operand<i64> {
+ let ParserMatchClass = SImmScaledMemoryIndexed<9, 16>;
+ let DecoderMethod = "DecodeSImm<9>";
+ let PrintMethod = "printImmScale<16>";
+}
+
// uimm6 predicate - True if the immediate is in the range [0, 63].
def UImm6Operand : AsmOperandClass {
let Name = "UImm6";
@@ -366,6 +372,7 @@ def UImm6s1Operand : UImmScaledMemoryInd
def UImm6s2Operand : UImmScaledMemoryIndexed<6, 2>;
def UImm6s4Operand : UImmScaledMemoryIndexed<6, 4>;
def UImm6s8Operand : UImmScaledMemoryIndexed<6, 8>;
+def UImm6s16Operand : UImmScaledMemoryIndexed<6, 16>;
def uimm6s1 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> {
let ParserMatchClass = UImm6s1Operand;
@@ -385,6 +392,11 @@ def uimm6s8 : Operand<i64>, ImmLeaf<i64,
let PrintMethod = "printImmScale<8>";
let ParserMatchClass = UImm6s8Operand;
}
+def uimm6s16 : Operand<i64>, ImmLeaf<i64,
+[{ return Imm >= 0 && Imm < (64*16) && ((Imm % 16) == 0); }]> {
+ let PrintMethod = "printImmScale<16>";
+ let ParserMatchClass = UImm6s16Operand;
+}
// simm6sN predicate - True if the immediate is a multiple of N in the range
// [-32 * N, 31 * N].
@@ -1740,10 +1752,12 @@ multiclass AddSubCarry<bit isSub, string
}
class BaseTwoOperand<bits<4> opc, RegisterClass regtype, string asm,
- SDPatternOperator OpNode>
- : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
+ SDPatternOperator OpNode,
+ RegisterClass in1regtype = regtype,
+ RegisterClass in2regtype = regtype>
+ : I<(outs regtype:$Rd), (ins in1regtype:$Rn, in2regtype:$Rm),
asm, "\t$Rd, $Rn, $Rm", "",
- [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]> {
+ [(set regtype:$Rd, (OpNode in1regtype:$Rn, in2regtype:$Rm))]> {
bits<5> Rd;
bits<5> Rn;
bits<5> Rm;
@@ -2009,7 +2023,6 @@ class BaseAddSubImm<bit isSub, bit setFl
let Inst{28-24} = 0b10001;
let Inst{9-5} = Rn;
let Inst{4-0} = Rd;
- let DecoderMethod = "DecodeBaseAddSubImm";
}
class AddSubImmShift<bit isSub, bit setFlags, RegisterClass dstRegtype,
@@ -2021,6 +2034,7 @@ class AddSubImmShift<bit isSub, bit setF
bits<14> imm;
let Inst{23-22} = imm{13-12}; // '00' => lsl #0, '01' => lsl #12
let Inst{21-10} = imm{11-0};
+ let DecoderMethod = "DecodeAddSubImmShift";
}
class BaseAddSubRegPseudo<RegisterClass regtype,
@@ -2298,6 +2312,27 @@ multiclass AddSubS<bit isSub, string mne
GPR64, GPR64sponly, GPR64, 24>; // UXTX #0
}
+class AddSubG<bit isSub, string asm_inst, SDPatternOperator OpNode>
+ : BaseAddSubImm<
+ isSub, 0, GPR64sp, asm_inst, "\t$Rd, $Rn, $imm6, $imm4",
+ (ins GPR64sp:$Rn, uimm6s16:$imm6, imm0_15:$imm4),
+ (set GPR64sp:$Rd, (OpNode GPR64sp:$Rn, imm0_63:$imm6, imm0_15:$imm4))> {
+ bits<6> imm6;
+ bits<4> imm4;
+ let Inst{31} = 1;
+ let Inst{23-22} = 0b10;
+ let Inst{21-16} = imm6;
+ let Inst{15-14} = 0b00;
+ let Inst{13-10} = imm4;
+ let Unpredictable{15-14} = 0b11;
+}
+
+class SUBP<bit setsFlags, string asm_instr, SDPatternOperator OpNode>
+ : BaseTwoOperand<0b0000, GPR64, asm_instr, null_frag, GPR64sp, GPR64sp> {
+ let Inst{31} = 1;
+ let Inst{29} = setsFlags;
+}
+
//---
// Extract
//---
@@ -3959,6 +3994,78 @@ class StoreExclusivePair<bits<2> sz, bit
let Constraints = "@earlyclobber $Ws";
}
+// Armv8.5-A Memory Tagging Extension
+class BaseMemTag<bits<2> opc1, bits<2> opc2, string asm_insn,
+ string asm_opnds, string cstr, dag oops, dag iops>
+ : I<oops, iops, asm_insn, asm_opnds, cstr, []>,
+ Sched<[]> {
+ bits<5> Rn;
+
+ let Inst{31-24} = 0b11011001;
+ let Inst{23-22} = opc1;
+ let Inst{21} = 1;
+ // Inst{20-12} defined by subclass
+ let Inst{11-10} = opc2;
+ let Inst{9-5} = Rn;
+ // Inst{4-0} defined by subclass
+}
+
+class MemTagVector<bit Load, string asm_insn, string asm_opnds,
+ dag oops, dag iops>
+ : BaseMemTag<{0b1, Load}, 0b00, asm_insn, asm_opnds,
+ "$Rn = $wback, at earlyclobber $wback", oops, iops> {
+ bits<5> Rt;
+
+ let Inst{20-12} = 0b000000000;
+ let Inst{4-0} = Rt;
+
+ let mayLoad = Load;
+}
+
+class MemTagLoad<string asm_insn, string asm_opnds>
+ : BaseMemTag<0b01, 0b00, asm_insn, asm_opnds, "", (outs GPR64:$Rt),
+ (ins GPR64sp:$Rn, simm9s16:$offset)> {
+ bits<5> Rt;
+ bits<9> offset;
+
+ let Inst{20-12} = offset;
+ let Inst{4-0} = Rt;
+
+ let mayLoad = 1;
+}
+
+class BaseMemTagStore<bits<2> opc1, bits<2> opc2, string asm_insn,
+ string asm_opnds, string cstr, dag oops, dag iops>
+ : BaseMemTag<opc1, opc2, asm_insn, asm_opnds, cstr, oops, iops> {
+ bits<5> Rt;
+ bits<9> offset;
+
+ let Inst{20-12} = offset;
+ let Inst{4-0} = 0b11111;
+ let Unpredictable{4-0} = 0b11111;
+
+ let mayStore = 1;
+}
+
+multiclass MemTagStore<bits<2> opc1, string insn> {
+ def Offset :
+ BaseMemTagStore<opc1, 0b10, insn, "\t[$Rn, $offset]", "",
+ (outs), (ins GPR64sp:$Rn, simm9s16:$offset)>;
+ def PreIndex :
+ BaseMemTagStore<opc1, 0b11, insn, "\t[$Rn, $offset]!",
+ "$Rn = $wback, at earlyclobber $wback",
+ (outs GPR64sp:$wback),
+ (ins GPR64sp:$Rn, simm9s16:$offset)>;
+ def PostIndex :
+ BaseMemTagStore<opc1, 0b01, insn, "\t[$Rn], $offset",
+ "$Rn = $wback, at earlyclobber $wback",
+ (outs GPR64sp:$wback),
+ (ins GPR64sp:$Rn, simm9s16:$offset)>;
+
+ def : InstAlias<insn # "\t[$Rn]",
+ (!cast<Instruction>(NAME # "Offset") GPR64sp:$Rn, 0)>;
+}
+
//---
// Exception generation
//---
Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td?rev=343572&r1=343571&r2=343572&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.td Tue Oct 2 03:04:39 2018
@@ -74,6 +74,8 @@ def HasCCDP : Predicate<"Subtar
AssemblerPredicate<"FeatureCacheDeepPersist", "ccdp">;
def HasBTI : Predicate<"Subtarget->hasBTI()">,
AssemblerPredicate<"FeatureBranchTargetId", "bti">;
+def HasMTE : Predicate<"Subtarget->hasMTE()">,
+ AssemblerPredicate<"FeatureMTE", "mte">;
def IsLE : Predicate<"Subtarget->isLittleEndian()">;
def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
def UseAlternateSExtLoadCVTF32
@@ -1123,6 +1125,50 @@ defm : STOPregister<"stsmin","LDSMIN">;/
defm : STOPregister<"stumax","LDUMAX">;// STUMAXx
defm : STOPregister<"stumin","LDUMIN">;// STUMINx
+// v8.5 Memory Tagging Extension
+let Predicates = [HasMTE] in {
+
+def IRG : BaseTwoOperand<0b0100, GPR64sp, "irg", null_frag, GPR64sp, GPR64>,
+ Sched<[]>{
+ let Inst{31} = 1;
+}
+def GMI : BaseTwoOperand<0b0101, GPR64, "gmi", null_frag, GPR64sp>, Sched<[]>{
+ let Inst{31} = 1;
+ let isNotDuplicable = 1;
+}
+def ADDG : AddSubG<0, "addg", null_frag>;
+def SUBG : AddSubG<1, "subg", null_frag>;
+
+def : InstAlias<"irg $dst, $src", (IRG GPR64sp:$dst, GPR64sp:$src, XZR), 1>;
+
+def SUBP : SUBP<0, "subp", null_frag>, Sched<[]>;
+def SUBPS : SUBP<1, "subps", null_frag>, Sched<[]>{
+ let Defs = [NZCV];
+}
+
+def : InstAlias<"cmpp $lhs, $rhs", (SUBPS XZR, GPR64sp:$lhs, GPR64sp:$rhs), 0>;
+
+def LDG : MemTagLoad<"ldg", "\t$Rt, [$Rn, $offset]">;
+def : InstAlias<"ldg $Rt, [$Rn]", (LDG GPR64:$Rt, GPR64sp:$Rn, 0), 1>;
+
+def LDGV : MemTagVector<1, "ldgv", "\t$Rt, [$Rn]!",
+ (outs GPR64sp:$wback, GPR64:$Rt), (ins GPR64sp:$Rn)> {
+ let DecoderMethod = "DecodeLoadAllocTagArrayInstruction";
+}
+def STGV : MemTagVector<0, "stgv", "\t$Rt, [$Rn]!",
+ (outs GPR64sp:$wback), (ins GPR64:$Rt, GPR64sp:$Rn)>;
+
+defm STG : MemTagStore<0b00, "stg">;
+defm STZG : MemTagStore<0b01, "stzg">;
+defm ST2G : MemTagStore<0b10, "st2g">;
+defm STZ2G : MemTagStore<0b11, "stz2g">;
+
+defm STGP : StorePairOffset <0b01, 0, GPR64z, simm7s16, "stgp">;
+def STGPpre : StorePairPreIdx <0b01, 0, GPR64z, simm7s16, "stgp">;
+def STGPpost : StorePairPostIdx<0b01, 0, GPR64z, simm7s16, "stgp">;
+
+} // Predicates = [HasMTE]
+
//===----------------------------------------------------------------------===//
// Logical instructions.
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h?rev=343572&r1=343571&r2=343572&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64Subtarget.h Tue Oct 2 03:04:39 2018
@@ -323,13 +323,13 @@ public:
bool hasAggressiveFMA() const { return HasAggressiveFMA; }
bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
bool hasFRInt3264() const { return HasFRInt3264; }
- bool hasSpecRestrict() { return HasSpecRestrict; }
- bool hasSpecCtrl() { return HasSpecCtrl; }
- bool hasPredCtrl() { return HasPredCtrl; }
- bool hasCCDP() { return HasCCDP; }
- bool hasBTI() { return HasBTI; }
- bool hasRandGen() { return HasRandGen; }
- bool hasMTE() { return HasMTE; }
+ bool hasSpecRestrict() const { return HasSpecRestrict; }
+ bool hasSpecCtrl() const { return HasSpecCtrl; }
+ bool hasPredCtrl() const { return HasPredCtrl; }
+ bool hasCCDP() const { return HasCCDP; }
+ bool hasBTI() const { return HasBTI; }
+ bool hasRandGen() const { return HasRandGen; }
+ bool hasMTE() const { return HasMTE; }
bool isLittleEndian() const { return IsLittle; }
Modified: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp?rev=343572&r1=343571&r2=343572&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp Tue Oct 2 03:04:39 2018
@@ -3826,13 +3826,9 @@ bool AArch64AsmParser::ParseInstruction(
// Read the remaining operands.
if (getLexer().isNot(AsmToken::EndOfStatement)) {
- // Read the first operand.
- if (parseOperand(Operands, false, false)) {
- return true;
- }
- unsigned N = 2;
- while (parseOptionalToken(AsmToken::Comma)) {
+ unsigned N = 1;
+ do {
// Parse and remember the operand.
if (parseOperand(Operands, (N == 4 && condCodeFourthOperand) ||
(N == 3 && condCodeThirdOperand) ||
@@ -3860,7 +3856,7 @@ bool AArch64AsmParser::ParseInstruction(
AArch64Operand::CreateToken("!", false, ELoc, getContext()));
++N;
- }
+ } while (parseOptionalToken(AsmToken::Comma));
}
if (parseToken(AsmToken::EndOfStatement, "unexpected token in argument list"))
@@ -4097,6 +4093,15 @@ bool AArch64AsmParser::validateInstructi
"unpredictable STXP instruction, status is also a source");
break;
}
+ case AArch64::LDGV: {
+ unsigned Rt = Inst.getOperand(0).getReg();
+ unsigned Rn = Inst.getOperand(1).getReg();
+ if (RI->isSubRegisterEq(Rt, Rn)) {
+ return Error(Loc[0],
+ "unpredictable LDGV instruction, writeback register is also "
+ "the target register");
+ }
+ }
}
@@ -4231,6 +4236,8 @@ bool AArch64AsmParser::showMatchError(SM
return Error(Loc, "index must be an integer in range [-128, 127].");
case Match_InvalidMemoryIndexedSImm9:
return Error(Loc, "index must be an integer in range [-256, 255].");
+ case Match_InvalidMemoryIndexed16SImm9:
+ return Error(Loc, "index must be a multiple of 16 in range [-4096, 4080].");
case Match_InvalidMemoryIndexed8SImm10:
return Error(Loc, "index must be a multiple of 8 in range [-4096, 4088].");
case Match_InvalidMemoryIndexed4SImm7:
@@ -4247,6 +4254,8 @@ bool AArch64AsmParser::showMatchError(SM
return Error(Loc, "index must be a multiple of 2 in range [0, 62].");
case Match_InvalidMemoryIndexed8UImm6:
return Error(Loc, "index must be a multiple of 8 in range [0, 504].");
+ case Match_InvalidMemoryIndexed16UImm6:
+ return Error(Loc, "index must be a multiple of 16 in range [0, 1008].");
case Match_InvalidMemoryIndexed4UImm6:
return Error(Loc, "index must be a multiple of 4 in range [0, 252].");
case Match_InvalidMemoryIndexed2UImm6:
@@ -4883,10 +4892,12 @@ bool AArch64AsmParser::MatchAndEmitInstr
case Match_InvalidMemoryIndexed2UImm6:
case Match_InvalidMemoryIndexed4UImm6:
case Match_InvalidMemoryIndexed8UImm6:
+ case Match_InvalidMemoryIndexed16UImm6:
case Match_InvalidMemoryIndexedSImm6:
case Match_InvalidMemoryIndexedSImm5:
case Match_InvalidMemoryIndexedSImm8:
case Match_InvalidMemoryIndexedSImm9:
+ case Match_InvalidMemoryIndexed16SImm9:
case Match_InvalidMemoryIndexed8SImm10:
case Match_InvalidImm0_1:
case Match_InvalidImm0_7:
Modified: llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp?rev=343572&r1=343571&r2=343572&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp Tue Oct 2 03:04:39 2018
@@ -160,8 +160,8 @@ static DecodeStatus DecodeModImmTiedInst
const void *Decoder);
static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn,
- uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
+ uint64_t Address, const void *Decoder);
static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
uint64_t Address,
const void *Decoder);
@@ -220,6 +220,11 @@ static DecodeStatus DecodeImm8OptLsl(MCI
static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
uint64_t Addr, const void *Decoder);
+static DecodeStatus DecodeLoadAllocTagArrayInstruction(MCInst &Inst,
+ uint32_t insn,
+ uint64_t address,
+ const void* Decoder);
+
static bool Check(DecodeStatus &Out, DecodeStatus In) {
switch (In) {
case MCDisassembler::Success:
@@ -1403,6 +1408,8 @@ static DecodeStatus DecodePairLdStInstru
case AArch64::STPSpost:
case AArch64::LDPSpre:
case AArch64::STPSpre:
+ case AArch64::STGPpre:
+ case AArch64::STGPpost:
DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
break;
}
@@ -1416,6 +1423,8 @@ static DecodeStatus DecodePairLdStInstru
case AArch64::LDPXpre:
case AArch64::STPXpre:
case AArch64::LDPSWpre:
+ case AArch64::STGPpre:
+ case AArch64::STGPpost:
NeedsDisjointWritebackTransfer = true;
LLVM_FALLTHROUGH;
case AArch64::LDNPXi:
@@ -1423,6 +1432,7 @@ static DecodeStatus DecodePairLdStInstru
case AArch64::LDPXi:
case AArch64::STPXi:
case AArch64::LDPSWi:
+ case AArch64::STGPi:
DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
DecodeGPR64RegisterClass(Inst, Rt2, Addr, Decoder);
break;
@@ -1653,8 +1663,8 @@ static DecodeStatus DecodeAdrInstruction
return Success;
}
-static DecodeStatus DecodeBaseAddSubImm(MCInst &Inst, uint32_t insn,
- uint64_t Addr, const void *Decoder) {
+static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
+ uint64_t Addr, const void *Decoder) {
unsigned Rd = fieldFromInstruction(insn, 0, 5);
unsigned Rn = fieldFromInstruction(insn, 5, 5);
unsigned Imm = fieldFromInstruction(insn, 10, 14);
@@ -1842,3 +1852,25 @@ static DecodeStatus DecodeSVEIncDecImm(M
Inst.addOperand(MCOperand::createImm(Imm + 1));
return Success;
}
+
+static DecodeStatus DecodeLoadAllocTagArrayInstruction(MCInst &Inst,
+ uint32_t insn,
+ uint64_t address,
+ const void* Decoder) {
+ unsigned Rn = fieldFromInstruction(insn, 5, 5);
+ unsigned Rt = fieldFromInstruction(insn, 0, 5);
+
+ // Outputs
+ DecodeGPR64spRegisterClass(Inst, Rn, address, Decoder);
+ DecodeGPR64RegisterClass(Inst, Rt, address, Decoder);
+
+ // Input (Rn again)
+ Inst.addOperand(Inst.getOperand(0));
+
+ //Do this post decode since the raw number for xzr and sp is the same
+ if (Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg()) {
+ return SoftFail;
+ } else {
+ return Success;
+ }
+}
Modified: llvm/trunk/test/MC/AArch64/armv8.5a-mte-error.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.5a-mte-error.s?rev=343572&r1=343571&r2=343572&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.5a-mte-error.s (original)
+++ llvm/trunk/test/MC/AArch64/armv8.5a-mte-error.s Tue Oct 2 03:04:39 2018
@@ -1,5 +1,550 @@
// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+mte < %s 2>&1| FileCheck %s
+irg
+irg x0
+irg q0, x0
+irg w0, x0
+irg x0, q0
+irg x0, w0
+irg x0, x1, q0
+irg x0, x1, w0
+irg x0, x1, sp
+irg x0, x1, #1
+irg x0, #1, x1
+irg #1, x0, x1
+irg x0, x1, x2, x3
+
+// CHECK: too few operands for instruction
+// CHECK-NEXT: irg
+// CHECK: too few operands for instruction
+// CHECK-NEXT: irg x0
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: irg q0, x0
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: irg w0, x0
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: irg x0, q0
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: irg x0, w0
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: irg x0, x1, q0
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: irg x0, x1, w0
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: irg x0, x1, sp
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: irg x0, x1, #1
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: irg x0, #1, x1
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: irg #1, x0, x1
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: irg x0, x1, x2, x3
+
+addg
+addg x0
+addg x0, x1
+addg x0, x1, #0
+addg x0, x1, #1024, #0
+addg x0, x1, #8, #0
+addg x0, x1, #-16, #0
+addg x0, x1, #0, #16
+addg q0, x1, #0, #0
+addg w0, x1, #0, #0
+addg x0, q1, #0, #0
+addg x0, w1, #0, #0
+addg #0, x1, #0, #0
+addg x0, #0, #0, #0
+addg x0, x1, x0, #0
+addg x0, x1, #0, x0
+addg x0, x1, #16, #2, #99
+
+subg
+subg x0
+subg x0, x1
+subg x0, x1, #0
+subg x0, x1, #1024, #0
+subg x0, x1, #8, #0
+subg x0, x1, #-16, #0
+subg x0, x1, #0, #16
+subg q0, x1, #0, #0
+subg w0, x1, #0, #0
+subg x0, q1, #0, #0
+subg x0, w1, #0, #0
+subg #0, x1, #0, #0
+subg x0, #0, #0, #0
+subg x0, x1, x0, #0
+subg x0, x1, #0, x0
+subg x0, x1, #16, #2, #99
+
+// CHECK: too few operands for instruction
+// CHECK-NEXT: addg
+// CHECK: too few operands for instruction
+// CHECK-NEXT: addg x0
+// CHECK: too few operands for instruction
+// CHECK-NEXT: addg x0, x1
+// CHECK: too few operands for instruction
+// CHECK-NEXT: addg x0, x1, #0
+// CHECK: index must be a multiple of 16 in range [0, 1008]
+// CHECK-NEXT: addg x0, x1, #1024, #0
+// CHECK: index must be a multiple of 16 in range [0, 1008]
+// CHECK-NEXT: addg x0, x1, #8, #0
+// CHECK: index must be a multiple of 16 in range [0, 1008]
+// CHECK-NEXT: addg x0, x1, #-16, #0
+// CHECK: immediate must be an integer in range [0, 15]
+// CHECK-NEXT: addg x0, x1, #0, #16
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: addg q0, x1, #0, #0
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: addg w0, x1, #0, #0
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: addg x0, q1, #0, #0
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: addg x0, w1, #0, #0
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: addg #0, x1, #0, #0
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: addg x0, #0, #0, #0
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: addg x0, x1, x0, #0
+// CHECK: immediate must be an integer in range [0, 15]
+// CHECK-NEXT: addg x0, x1, #0, x0
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: addg x0, x1, #16, #2, #99
+
+// CHECK: too few operands for instruction
+// CHECK-NEXT: subg
+// CHECK: too few operands for instruction
+// CHECK-NEXT: subg x0
+// CHECK: too few operands for instruction
+// CHECK-NEXT: subg x0, x1
+// CHECK: too few operands for instruction
+// CHECK-NEXT: subg x0, x1, #0
+// CHECK: index must be a multiple of 16 in range [0, 1008]
+// CHECK-NEXT: subg x0, x1, #1024, #0
+// CHECK: index must be a multiple of 16 in range [0, 1008]
+// CHECK-NEXT: subg x0, x1, #8, #0
+// CHECK: index must be a multiple of 16 in range [0, 1008]
+// CHECK-NEXT: subg x0, x1, #-16, #0
+// CHECK: immediate must be an integer in range [0, 15]
+// CHECK-NEXT: subg x0, x1, #0, #16
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: subg q0, x1, #0, #0
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: subg w0, x1, #0, #0
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: subg x0, q1, #0, #0
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: subg x0, w1, #0, #0
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: subg #0, x1, #0, #0
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: subg x0, #0, #0, #0
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: subg x0, x1, x0, #0
+// CHECK: immediate must be an integer in range [0, 15]
+// CHECK-NEXT: subg x0, x1, #0, x0
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: subg x0, x1, #16, #2, #99
+
+gmi
+gmi x0
+gmi x0, x1
+gmi sp, x0, x1
+gmi x0, x1, sp
+gmi x0, x1, x2, #1
+gmi w0, x1, x2
+gmi x0, w1, x2
+gmi x0, x1, w2
+gmi #1, x1, x2
+gmi x0, #1, x2
+gmi x0, x1, #1
+
+// CHECK: too few operands for instruction
+// CHECK-NEXT: gmi
+// CHECK: too few operands for instruction
+// CHECK-NEXT: gmi x0
+// CHECK: too few operands for instruction
+// CHECK-NEXT: gmi x0, x1
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: gmi sp, x0, x1
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: gmi x0, x1, sp
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: gmi x0, x1, x2, #1
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: gmi w0, x1, x2
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: gmi x0, w1, x2
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: gmi x0, x1, w2
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: gmi #1, x1, x2
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: gmi x0, #1, x2
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: gmi x0, x1, #1
+
+stg
+stg x0
+stg [xzr]
+stg [x0, #-4112]
+stg [x0, #4096]
+stg [x0, #8]
+stg [x0, x1]
+stg [w0]
+
+// CHECK: too few operands for instruction
+// CHECK-NEXT: stg
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stg x0
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: [xzr]
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #-4112
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #4096
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #8
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stg [x0, x1]
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stg [w0]
+
+stzg
+stzg x0
+stzg [xzr]
+stzg [x0, #-4112]
+stzg [x0, #4096]
+stzg [x0, #8]
+stzg [x0, x1]
+stzg [w0]
+
+// CHECK: too few operands for instruction
+// CHECK-NEXT: stzg
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stzg x0
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: [xzr]
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #-4112
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #4096
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #8
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stzg [x0, x1]
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stzg [w0]
+
+stg [x0, #-4112]!
+stg [x0, #4096]!
+stg [x0, #8]!
+stg [x0, x1]!
+stg [w0, #255]!
+
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #-4112
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #4096
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #8
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stg [x0, x1]!
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stg [w0, #255]!
+
+stzg [x0, #-4112]!
+stzg [x0, #4096]!
+stzg [x0, #8]!
+stzg [x0, x1]!
+stzg [w0, #255]!
+
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #-4112
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #4096
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #8
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stzg [x0, x1]!
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stzg [w0, #255]!
+
+stg [x0], #-4112
+stg [x0], #4096
+stg [x0], #8
+stg [x0], x1
+stg [w0], #255
+
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #-4112
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #4096
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #8
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stg [x0], x1
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stg [w0], #255
+
+stzg [x0], #-4112
+stzg [x0], #4096
+stzg [x0], #8
+stzg [x0], x1
+stzg [w0], #255
+
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #-4112
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #4096
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #8
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stzg [x0], x1
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stzg [w0], #255
+
+st2g
+st2g x0
+st2g [xzr]
+st2g [x0, #-4112]
+st2g [x0, #4096]
+st2g [x0, #8]
+st2g [x0, x1]
+st2g [w0]
+
+// CHECK: too few operands for instruction
+// CHECK-NEXT: st2g
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: st2g x0
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: [xzr]
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #-4112
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #4096
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #8
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: st2g [x0, x1]
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: st2g [w0]
+
+stz2g
+stz2g [xzr]
+stz2g [x0, #-4112]
+stz2g [x0, #4096]
+stz2g [x0, #8]
+stz2g [x0, x1]
+stz2g [w0]
+
+// CHECK: too few operands for instruction
+// CHECK-NEXT: stz2g
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: [xzr]
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #-4112
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #4096
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #8
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stz2g [x0, x1]
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stz2g [w0]
+
+st2g [x0, #-4112]!
+st2g [x0, #4096]!
+st2g [x0, #8]!
+st2g [x0, x1]!
+st2g [w0, #255]!
+
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #-4112
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #4096
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #8
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: st2g [x0, x1]!
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: st2g [w0, #255]!
+
+stz2g [x0, #-4112]!
+stz2g [x0, #4096]!
+stz2g [x0, #8]!
+stz2g [x0, x1]!
+stz2g [w0, #255]!
+
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #-4112
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #4096
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #8
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stz2g [x0, x1]!
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stz2g [w0, #255]!
+
+st2g [x0], #-4112
+st2g [x0], #4096
+st2g [x0], #8
+st2g [x0], x1
+st2g [#1], #255
+
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #-4112
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #4096
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #8
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: st2g [x0], x1
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: st2g [#1], #255
+
+stz2g [x0], #-4112
+stz2g [x0], #4096
+stz2g [x0], #8
+stz2g [x0], x1
+stz2g [#0], x1
+
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #-4112
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #4096
+// CHECK: index must be a multiple of 16 in range [-4096, 4080]
+// CHECK-NEXT: #8
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stz2g [x0], x1
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stz2g [#0], x1
+
+stgp sp, x1, [x2, #16]
+stgp x0, sp, [x2, #16]
+stgp x0, x1, [xzr, #16]
+stgp x0, x1, [x2, #-1040]
+stgp x0, x1, [x2, #1024]
+stgp x0, x1, [x2, #8]
+stgp x0, x1, [x2, x3]
+stgp w0, x1, [x2, #1]
+stgp x0, w1, [x2, #1]
+stgp x0, x1, [w2, #1]
+stgp #1, x1, [x3, #1]
+stgp x0, #1, [x3, #1]
+stgp x0, x1, [#1, #1]
+
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp sp
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp x0, sp
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp x0, x1, [xzr
+// CHECK: index must be a multiple of 16 in range [-1024, 1008]
+// CHECK-NEXT: #-1040
+// CHECK: index must be a multiple of 16 in range [-1024, 1008]
+// CHECK-NEXT: #1024
+// CHECK: index must be a multiple of 16 in range [-1024, 1008]
+// CHECK-NEXT: #8
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp x0, x1, [x2, x3]
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp w0, x1, [x2, #1]
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp x0, w1, [x2, #1]
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp x0, x1, [w2, #1]
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp #1, x1, [x3, #1]
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp x0, #1, [x3, #1]
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp x0, x1, [#1, #1]
+
+stgp sp, x1, [x2, #16]!
+stgp x0, sp, [x2, #16]!
+stgp x0, x1, [xzr, #16]!
+stgp x0, x1, [x2, #-1040]!
+stgp x0, x1, [x2, #1024]!
+stgp x0, x1, [x2, #8]!
+stgp x0, x1, [x2, x3]!
+stgp w0, x1, [x2, #1]!
+stgp x0, w1, [x2, #1]!
+stgp x0, x1, [w2, #1]!
+stgp #1, x1, [x3, #1]!
+stgp x0, #1, [x3, #1]!
+stgp x0, x1, [#1, #1]!
+
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp sp
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp x0, sp
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp x0, x1, [xzr
+// CHECK: index must be a multiple of 16 in range [-1024, 1008]
+// CHECK-NEXT: #-1040
+// CHECK: index must be a multiple of 16 in range [-1024, 1008]
+// CHECK-NEXT: #1024
+// CHECK: index must be a multiple of 16 in range [-1024, 1008]
+// CHECK-NEXT: #8
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp x0, x1, [x2, x3]!
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp w0, x1, [x2, #1]!
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp x0, w1, [x2, #1]!
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp x0, x1, [w2, #1]!
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp #1, x1, [x3, #1]!
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp x0, #1, [x3, #1]!
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp x0, x1, [#1, #1]!
+
+stgp sp, x1, [x2], #16
+stgp x0, sp, [x2], #16
+stgp x0, x1, [xzr], #16
+stgp x0, x1, [x2], #-1040
+stgp x0, x1, [x2], #1024
+stgp x0, x1, [x2], #8
+stgp x0, x1, [x2], x3
+stgp w0, x1, [x2], #1
+stgp x0, w1, [x2], #1
+stgp x0, x1, [w2], #1
+stgp #1, x1, [x2], #1
+stgp x0, #1, [x2], #1
+stgp x0, x1, [#1], #1
+
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp sp
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp x0, sp
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp x0, x1, [xzr
+// CHECK: index must be a multiple of 16 in range [-1024, 1008]
+// CHECK-NEXT: #-1040
+// CHECK: index must be a multiple of 16 in range [-1024, 1008]
+// CHECK-NEXT: #1024
+// CHECK: index must be a multiple of 16 in range [-1024, 1008]
+// CHECK-NEXT: #8
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp x0, x1, [x2], x3
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp w0, x1, [x2], #1
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp x0, w1, [x2], #1
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp x0, x1, [w2], #1
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp #1, x1, [x2], #1
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp x0, #1, [x2], #1
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgp x0, x1, [#1], #1
+
mrs tco
mrs gcr_el1
mrs rgsr_el1
@@ -131,3 +676,174 @@ msr tfsre0_el1, #7
// CHECK-NEXT: tfsr_el12
// CHECK: invalid operand for instruction
// CHECK-NEXT: tfsre0_el1
+
+// Xd cannot be the stack pointer, the rest can
+subps sp, x0, x1
+subp sp, x2, x3
+subp w0, x1, x2
+subp x0, w1, x2
+subp x0, x1, w2
+subps w0, x1, x2
+subps x0, w1, x2
+subps x0, x1, w2
+subp #1, x1, x2
+subp x0, #1, x2
+subp x0, x1, #1
+subps #1, x1, x2
+subps x0, #1, x2
+subps x0, x1, #1
+
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: sp
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: sp
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: subp w0, x1, x2
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: subp x0, w1, x2
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: subp x0, x1, w2
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: subps w0, x1, x2
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: subps x0, w1, x2
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: subps x0, x1, w2
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: subp #1, x1, x2
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: subp x0, #1, x2
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: subp x0, x1, #1
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: subps #1, x1, x2
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: subps x0, #1, x2
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: subps x0, x1, #1
+
+subps x0, x1, x2, x3
+subp x0, x1, x2, x3
+
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: subps x0, x1, x2, x3
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: subp x0, x1, x2, x3
+
+subps
+subp
+cmpp
+subps x0
+subp x0
+cmpp x0
+subps x0, x1
+subp x0, x1
+
+// CHECK: too few operands for instruction
+// CHECK-NEXT: subps
+// CHECK: too few operands for instruction
+// CHECK-NEXT: subp
+// CHECK: too few operands for instruction
+// CHECK-NEXT: cmpp
+// CHECK: too few operands for instruction
+// CHECK-NEXT: subps x0
+// CHECK: too few operands for instruction
+// CHECK-NEXT: subp x0
+// CHECK: too few operands for instruction
+// CHECK-NEXT: cmpp x0
+// CHECK: too few operands for instruction
+// CHECK-NEXT: subps x0, x1
+// CHECK: too few operands for instruction
+// CHECK-NEXT: subp x0, x1
+
+ldg sp, [x0, #0]
+ldg x0, [x0, x0]
+ldg x0, [x0, #4096]
+ldg x0, [x0, #-4112]
+ldg #1, [x0, #255]
+ldg x0, [#1, #255]
+
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: ldg sp, [x0, #0]
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: ldg x0, [x0, x0]
+// CHECK: index must be a multiple of 16 in range [-4096, 4080].
+// CHECK-NEXT: ldg x0, [x0, #4096]
+// CHECK: index must be a multiple of 16 in range [-4096, 4080].
+// CHECK-NEXT: ldg x0, [x0, #-4112]
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: ldg #1, [x0, #255]
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: ldg x0, [#1, #255]
+
+ldg
+ldg x0
+ldg x0, [#0]
+ldg w0, [x1]
+ldg x0, [w1]
+
+// CHECK: too few operands for instruction
+// CHECK-NEXT: ldg
+// CHECK: too few operands for instruction
+// CHECK-NEXT: ldg x0
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: ldg x0, [#0]
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: ldg w0, [x1]
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: ldg x0, [w1]
+
+ldgv
+ldgv x0
+ldgv x0, [x1]
+ldgv sp, [x0]!
+ldgv x3, [x3]!
+ldgv w0, [x1]!
+ldgv x0, [w1]!
+ldgv #1, [x1]!
+ldgv x0, [#1]!
+
+// CHECK: too few operands for instruction
+// CHECK-NEXT: ldgv
+// CHECK: too few operands for instruction
+// CHECK-NEXT: ldgv x0
+// CHECK: too few operands for instruction
+// CHECK-NEXT: ldgv x0, [x1]
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: ldgv sp, [x0]!
+// CHECK: unpredictable LDGV instruction, writeback register is also the target register
+// CHECK-NEXT: ldgv x3, [x3]!
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: ldgv w0, [x1]!
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: ldgv x0, [w1]!
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: ldgv #1, [x1]!
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: ldgv x0, [#1]!
+
+stgv
+stgv x0
+stgv x0, [x1]
+stgv sp, [x0]!
+stgv w0, [x0]!
+stgv x0, [w0]!
+stgv #1, [x1]!
+stgv x0, [#1]!
+
+// CHECK: too few operands for instruction
+// CHECK-NEXT: stgv
+// CHECK: too few operands for instruction
+// CHECK-NEXT: stgv x0
+// CHECK: too few operands for instruction
+// CHECK-NEXT: stgv x0, [x1]
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgv sp, [x0]!
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgv w0, [x0]!
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgv x0, [w0]!
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgv #1, [x1]!
+// CHECK: invalid operand for instruction
+// CHECK-NEXT: stgv x0, [#1]!
Modified: llvm/trunk/test/MC/AArch64/armv8.5a-mte.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/armv8.5a-mte.s?rev=343572&r1=343571&r2=343572&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/armv8.5a-mte.s (original)
+++ llvm/trunk/test/MC/AArch64/armv8.5a-mte.s Tue Oct 2 03:04:39 2018
@@ -2,6 +2,359 @@
// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s 2>&1 | FileCheck %s --check-prefix=NOMTE
// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-mte < %s 2>&1 | FileCheck %s --check-prefix=NOMTE
+irg x0, x1
+irg sp, x1
+irg x0, sp
+irg x0, x1, x2
+irg sp, x1, x2
+
+// CHECK: irg x0, x1 // encoding: [0x20,0x10,0xdf,0x9a]
+// CHECK: irg sp, x1 // encoding: [0x3f,0x10,0xdf,0x9a]
+// CHECK: irg x0, sp // encoding: [0xe0,0x13,0xdf,0x9a]
+// CHECK: irg x0, x1, x2 // encoding: [0x20,0x10,0xc2,0x9a]
+// CHECK: irg sp, x1, x2 // encoding: [0x3f,0x10,0xc2,0x9a]
+
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: irg x0, x1
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: irg sp, x1
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: irg x0, sp
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: irg x0, x1, x2
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: irg sp, x1, x2
+
+addg x0, x1, #0, #1
+addg sp, x2, #32, #3
+addg x0, sp, #64, #5
+addg x3, x4, #1008, #6
+addg x5, x6, #112, #15
+
+subg x0, x1, #0, #1
+subg sp, x2, #32, #3
+subg x0, sp, #64, #5
+subg x3, x4, #1008, #6
+subg x5, x6, #112, #15
+
+// CHECK: addg x0, x1, #0, #1 // encoding: [0x20,0x04,0x80,0x91]
+// CHECK: addg sp, x2, #32, #3 // encoding: [0x5f,0x0c,0x82,0x91]
+// CHECK: addg x0, sp, #64, #5 // encoding: [0xe0,0x17,0x84,0x91]
+// CHECK: addg x3, x4, #1008, #6 // encoding: [0x83,0x18,0xbf,0x91]
+// CHECK: addg x5, x6, #112, #15 // encoding: [0xc5,0x3c,0x87,0x91]
+
+// CHECK: subg x0, x1, #0, #1 // encoding: [0x20,0x04,0x80,0xd1]
+// CHECK: subg sp, x2, #32, #3 // encoding: [0x5f,0x0c,0x82,0xd1]
+// CHECK: subg x0, sp, #64, #5 // encoding: [0xe0,0x17,0x84,0xd1]
+// CHECK: subg x3, x4, #1008, #6 // encoding: [0x83,0x18,0xbf,0xd1]
+// CHECK: subg x5, x6, #112, #15 // encoding: [0xc5,0x3c,0x87,0xd1]
+
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: addg x0, x1, #0, #1
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: addg sp, x2, #32, #3
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: addg x0, sp, #64, #5
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: addg x3, x4, #1008, #6
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: addg x5, x6, #112, #15
+
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: subg x0, x1, #0, #1
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: subg sp, x2, #32, #3
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: subg x0, sp, #64, #5
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: subg x3, x4, #1008, #6
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: subg x5, x6, #112, #15
+
+gmi x0, x1, x2
+gmi x3, sp, x4
+gmi xzr, x0, x30
+gmi x30, x0, xzr
+
+// CHECK: gmi x0, x1, x2 // encoding: [0x20,0x14,0xc2,0x9a]
+// CHECK: gmi x3, sp, x4 // encoding: [0xe3,0x17,0xc4,0x9a]
+// CHECK: gmi xzr, x0, x30 // encoding: [0x1f,0x14,0xde,0x9a]
+// CHECK: gmi x30, x0, xzr // encoding: [0x1e,0x14,0xdf,0x9a]
+
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: gmi x0, x1, x2
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: gmi x3, sp, x4
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: gmi xzr, x0, x30
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: gmi x30, x0, xzr
+
+stg [x1]
+stg [x1, #-4096]
+stg [x2, #4080]
+stg [sp, #16]
+
+// CHECK: stg [x1] // encoding: [0x3f,0x08,0x20,0xd9]
+// CHECK: stg [x1, #-4096] // encoding: [0x3f,0x08,0x30,0xd9]
+// CHECK: stg [x2, #4080] // encoding: [0x5f,0xf8,0x2f,0xd9]
+// CHECK: stg [sp, #16] // encoding: [0xff,0x1b,0x20,0xd9]
+
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stg
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stg
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stg
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stg
+
+stzg [x1]
+stzg [x1, #-4096]
+stzg [x2, #4080]
+stzg [sp, #16]
+
+// CHECK: stzg [x1] // encoding: [0x3f,0x08,0x60,0xd9]
+// CHECK: stzg [x1, #-4096] // encoding: [0x3f,0x08,0x70,0xd9]
+// CHECK: stzg [x2, #4080] // encoding: [0x5f,0xf8,0x6f,0xd9]
+// CHECK: stzg [sp, #16] // encoding: [0xff,0x1b,0x60,0xd9]
+
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stzg
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stzg
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stzg
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stzg
+
+stg [x1, #-4096]!
+stg [x2, #4080]!
+stg [sp, #16]!
+
+// CHECK: stg [x1, #-4096]! // encoding: [0x3f,0x0c,0x30,0xd9]
+// CHECK: stg [x2, #4080]! // encoding: [0x5f,0xfc,0x2f,0xd9]
+// CHECK: stg [sp, #16]! // encoding: [0xff,0x1f,0x20,0xd9]
+
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stg
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stg
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stg
+
+stzg [x1, #-4096]!
+stzg [x2, #4080]!
+stzg [sp, #16]!
+
+// CHECK: stzg [x1, #-4096]! // encoding: [0x3f,0x0c,0x70,0xd9]
+// CHECK: stzg [x2, #4080]! // encoding: [0x5f,0xfc,0x6f,0xd9]
+// CHECK: stzg [sp, #16]! // encoding: [0xff,0x1f,0x60,0xd9]
+
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stzg
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stzg
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stzg
+
+stg [x1], #-4096
+stg [x2], #4080
+stg [sp], #16
+
+// CHECK: stg [x1], #-4096 // encoding: [0x3f,0x04,0x30,0xd9]
+// CHECK: stg [x2], #4080 // encoding: [0x5f,0xf4,0x2f,0xd9]
+// CHECK: stg [sp], #16 // encoding: [0xff,0x17,0x20,0xd9]
+
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stg
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stg
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stg
+
+stzg [x1], #-4096
+stzg [x2], #4080
+stzg [sp], #16
+
+// CHECK: stzg [x1], #-4096 // encoding: [0x3f,0x04,0x70,0xd9]
+// CHECK: stzg [x2], #4080 // encoding: [0x5f,0xf4,0x6f,0xd9]
+// CHECK: stzg [sp], #16 // encoding: [0xff,0x17,0x60,0xd9]
+
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stzg
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stzg
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stzg
+
+st2g [x1]
+st2g [x1, #-4096]
+st2g [x2, #4080]
+st2g [sp, #16]
+
+// CHECK: st2g [x1] // encoding: [0x3f,0x08,0xa0,0xd9]
+// CHECK: st2g [x1, #-4096] // encoding: [0x3f,0x08,0xb0,0xd9]
+// CHECK: st2g [x2, #4080] // encoding: [0x5f,0xf8,0xaf,0xd9]
+// CHECK: st2g [sp, #16] // encoding: [0xff,0x1b,0xa0,0xd9]
+
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: st2g
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: st2g
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: st2g
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: st2g
+
+stz2g [x1]
+stz2g [x1, #-4096]
+stz2g [x2, #4080]
+stz2g [sp, #16]
+
+// CHECK: stz2g [x1] // encoding: [0x3f,0x08,0xe0,0xd9]
+// CHECK: stz2g [x1, #-4096] // encoding: [0x3f,0x08,0xf0,0xd9]
+// CHECK: stz2g [x2, #4080] // encoding: [0x5f,0xf8,0xef,0xd9]
+// CHECK: stz2g [sp, #16] // encoding: [0xff,0x1b,0xe0,0xd9]
+
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stz2g
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stz2g
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stz2g
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stz2g
+
+st2g [x1, #-4096]!
+st2g [x2, #4080]!
+st2g [sp, #16]!
+
+// CHECK: st2g [x1, #-4096]! // encoding: [0x3f,0x0c,0xb0,0xd9]
+// CHECK: st2g [x2, #4080]! // encoding: [0x5f,0xfc,0xaf,0xd9]
+// CHECK: st2g [sp, #16]! // encoding: [0xff,0x1f,0xa0,0xd9]
+
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: st2g
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: st2g
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: st2g
+
+stz2g [x1, #-4096]!
+stz2g [x2, #4080]!
+stz2g [sp, #16]!
+
+// CHECK: stz2g [x1, #-4096]! // encoding: [0x3f,0x0c,0xf0,0xd9]
+// CHECK: stz2g [x2, #4080]! // encoding: [0x5f,0xfc,0xef,0xd9]
+// CHECK: stz2g [sp, #16]! // encoding: [0xff,0x1f,0xe0,0xd9]
+
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stz2g
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stz2g
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stz2g
+
+st2g [x1], #-4096
+st2g [x2], #4080
+st2g [sp], #16
+
+// CHECK: st2g [x1], #-4096 // encoding: [0x3f,0x04,0xb0,0xd9]
+// CHECK: st2g [x2], #4080 // encoding: [0x5f,0xf4,0xaf,0xd9]
+// CHECK: st2g [sp], #16 // encoding: [0xff,0x17,0xa0,0xd9]
+
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: st2g
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: st2g
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: st2g
+
+stz2g [x1], #-4096
+stz2g [x2], #4080
+stz2g [sp], #16
+
+// CHECK: stz2g [x1], #-4096 // encoding: [0x3f,0x04,0xf0,0xd9]
+// CHECK: stz2g [x2], #4080 // encoding: [0x5f,0xf4,0xef,0xd9]
+// CHECK: stz2g [sp], #16 // encoding: [0xff,0x17,0xe0,0xd9]
+
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stz2g
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stz2g
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stz2g
+
+stgp x0, x1, [x2]
+stgp x0, x1, [x2, #-1024]
+stgp x0, x1, [x2, #1008]
+stgp x0, x1, [sp, #16]
+stgp xzr, x1, [x2, #16]
+stgp x0, xzr, [x2, #16]
+
+// CHECK: stgp x0, x1, [x2] // encoding: [0x40,0x04,0x00,0x69]
+// CHECK: stgp x0, x1, [x2, #-1024] // encoding: [0x40,0x04,0x20,0x69]
+// CHECK: stgp x0, x1, [x2, #1008] // encoding: [0x40,0x84,0x1f,0x69]
+// CHECK: stgp x0, x1, [sp, #16] // encoding: [0xe0,0x87,0x00,0x69]
+// CHECK: stgp xzr, x1, [x2, #16] // encoding: [0x5f,0x84,0x00,0x69]
+// CHECK: stgp x0, xzr, [x2, #16] // encoding: [0x40,0xfc,0x00,0x69]
+
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stgp
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stgp
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stgp
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stgp
+
+stgp x0, x1, [x2, #-1024]!
+stgp x0, x1, [x2, #1008]!
+stgp x0, x1, [sp, #16]!
+stgp xzr, x1, [x2, #16]!
+stgp x0, xzr, [x2, #16]!
+
+// CHECK: stgp x0, x1, [x2, #-1024]! // encoding: [0x40,0x04,0xa0,0x69]
+// CHECK: stgp x0, x1, [x2, #1008]! // encoding: [0x40,0x84,0x9f,0x69]
+// CHECK: stgp x0, x1, [sp, #16]! // encoding: [0xe0,0x87,0x80,0x69]
+// CHECK: stgp xzr, x1, [x2, #16]! // encoding: [0x5f,0x84,0x80,0x69]
+// CHECK: stgp x0, xzr, [x2, #16]! // encoding: [0x40,0xfc,0x80,0x69]
+
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stgp
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stgp
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stgp
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stgp
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stgp
+
+stgp x0, x1, [x2], #-1024
+stgp x0, x1, [x2], #1008
+stgp x0, x1, [sp], #16
+stgp xzr, x1, [x2], #16
+stgp x0, xzr, [x2], #16
+
+// CHECK: stgp x0, x1, [x2], #-1024 // encoding: [0x40,0x04,0xa0,0x68]
+// CHECK: stgp x0, x1, [x2], #1008 // encoding: [0x40,0x84,0x9f,0x68]
+// CHECK: stgp x0, x1, [sp], #16 // encoding: [0xe0,0x87,0x80,0x68]
+// CHECK: stgp xzr, x1, [x2], #16 // encoding: [0x5f,0x84,0x80,0x68]
+// CHECK: stgp x0, xzr, [x2], #16 // encoding: [0x40,0xfc,0x80,0x68]
+
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stgp
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stgp
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stgp
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stgp
+// NOMTE: instruction requires: mte
+// NOMTE-NEXT: stgp
+
dc igvac, x0
dc igsw, x1
dc cgsw, x2
@@ -135,3 +488,66 @@ msr tfsre0_el1, x7
// NOMTE-NEXT: tfsr_el12
// NOMTE: expected writable system register or pstate
// NOMTE-NEXT: tfsre0_el1
+
+subp x0, x1, x2
+subp x0, sp, sp
+subps x0, x1, x2
+subps x0, sp, sp
+
+// CHECK: subp x0, x1, x2 // encoding: [0x20,0x00,0xc2,0x9a]
+// CHECK: subp x0, sp, sp // encoding: [0xe0,0x03,0xdf,0x9a]
+// CHECK: subps x0, x1, x2 // encoding: [0x20,0x00,0xc2,0xba]
+// CHECK: subps x0, sp, sp // encoding: [0xe0,0x03,0xdf,0xba]
+
+// NOMTE: instruction requires: mte
+// NOMTE: instruction requires: mte
+// NOMTE: instruction requires: mte
+
+subps xzr, x0, x1
+cmpp x0, x1
+subps xzr, sp, sp
+cmpp sp, sp
+
+// CHECK: subps xzr, x0, x1 // encoding: [0x1f,0x00,0xc1,0xba]
+// CHECK: subps xzr, x0, x1 // encoding: [0x1f,0x00,0xc1,0xba]
+// CHECK: subps xzr, sp, sp // encoding: [0xff,0x03,0xdf,0xba]
+// CHECK: subps xzr, sp, sp // encoding: [0xff,0x03,0xdf,0xba]
+
+// NOMTE: instruction requires: mte
+// NOMTE: instruction requires: mte
+// NOMTE: instruction requires: mte
+// NOMTE: instruction requires: mte
+
+ldg X0, [X1, #0]
+ldg X2, [sp, #-4096]
+ldg x3, [x4, #4080]
+
+// CHECK: ldg x0, [x1] // encoding: [0x20,0x00,0x60,0xd9]
+// CHECK: ldg x2, [sp, #-4096] // encoding: [0xe2,0x03,0x70,0xd9]
+// CHECK: ldg x3, [x4, #4080] // encoding: [0x83,0xf0,0x6f,0xd9]
+
+// NOMTE: instruction requires: mte
+// NOMTE: instruction requires: mte
+// NOMTE: instruction requires: mte
+
+ldgv x0, [x1]!
+ldgv x1, [sp]!
+ldgv xzr, [x2]!
+
+// CHECK: ldgv x0, [x1]! // encoding: [0x20,0x00,0xe0,0xd9]
+// CHECK: ldgv x1, [sp]! // encoding: [0xe1,0x03,0xe0,0xd9]
+// CHECK: ldgv xzr, [x2]! // encoding: [0x5f,0x00,0xe0,0xd9]
+
+// NOMTE: instruction requires: mte
+// NOMTE: instruction requires: mte
+
+stgv x0, [x1]!
+stgv x1, [sp]!
+stgv xzr, [x2]!
+
+// CHECK: stgv x0, [x1]! // encoding: [0x20,0x00,0xa0,0xd9]
+// CHECK: stgv x1, [sp]! // encoding: [0xe1,0x03,0xa0,0xd9]
+// CHECK: stgv xzr, [x2]! // encoding: [0x5f,0x00,0xa0,0xd9]
+
+// NOMTE: instruction requires: mte
+// NOMTE: instruction requires: mte
Added: llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-mte-unpredictable.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-mte-unpredictable.txt?rev=343572&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-mte-unpredictable.txt (added)
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-mte-unpredictable.txt Tue Oct 2 03:04:39 2018
@@ -0,0 +1,7 @@
+# RUN: llvm-mc -triple=aarch64 -mattr=+mte -disassemble < %s 2>&1 | FileCheck %s
+
+# ldgv x1, [x1]!
+[0x21,0x00,0xe0,0xd9]
+
+# CHECK: warning: potentially undefined instruction encoding
+# CHECK-NEXT: [0x21,0x00,0xe0,0xd9]
Modified: llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-mte.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-mte.txt?rev=343572&r1=343571&r2=343572&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-mte.txt (original)
+++ llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-mte.txt Tue Oct 2 03:04:39 2018
@@ -1,6 +1,432 @@
-# RUN: llvm-mc -triple=aarch64 -mattr=+mte -disassemble < %s | FileCheck %s
-# RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s --check-prefix=NOMTE
-# RUN: llvm-mc -triple=aarch64 -mattr=-mte -disassemble < %s | FileCheck %s --check-prefix=NOMTE
+# RUN: llvm-mc -triple=aarch64 -mattr=+mte -disassemble < %s | FileCheck %s
+# RUN: not llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOMTE
+# RUN: not llvm-mc -triple=aarch64 -mattr=-mte -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOMTE
+
+[0x20,0x10,0xdf,0x9a]
+[0x3f,0x10,0xdf,0x9a]
+[0xe0,0x13,0xdf,0x9a]
+[0x20,0x10,0xc2,0x9a]
+[0x3f,0x10,0xc2,0x9a]
+
+# CHECK: irg x0, x1
+# CHECK: irg sp, x1
+# CHECK: irg x0, sp
+# CHECK: irg x0, x1, x2
+# CHECK: irg sp, x1, x2
+
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x20,0x10,0xdf,0x9a]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x3f,0x10,0xdf,0x9a]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xe0,0x13,0xdf,0x9a]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x20,0x10,0xc2,0x9a]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x3f,0x10,0xc2,0x9a]
+
+[0x20,0x04,0x80,0x91]
+[0x5f,0x0c,0x82,0x91]
+[0xe0,0x17,0x84,0x91]
+[0x83,0x18,0xbf,0x91]
+[0xc5,0x3c,0x87,0x91]
+
+[0x20,0x04,0x80,0xd1]
+[0x5f,0x0c,0x82,0xd1]
+[0xe0,0x17,0x84,0xd1]
+[0x83,0x18,0xbf,0xd1]
+[0xc5,0x3c,0x87,0xd1]
+
+# CHECK: addg x0, x1, #0, #1
+# CHECK: addg sp, x2, #32, #3
+# CHECK: addg x0, sp, #64, #5
+# CHECK: addg x3, x4, #1008, #6
+# CHECK: addg x5, x6, #112, #15
+
+# CHECK: subg x0, x1, #0, #1
+# CHECK: subg sp, x2, #32, #3
+# CHECK: subg x0, sp, #64, #5
+# CHECK: subg x3, x4, #1008, #6
+# CHECK: subg x5, x6, #112, #15
+
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x20,0x04,0x80,0x91]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x5f,0x0c,0x82,0x91]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xe0,0x17,0x84,0x91]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x83,0x18,0xbf,0x91]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xc5,0x3c,0x87,0x91]
+
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x20,0x04,0x80,0xd1]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x5f,0x0c,0x82,0xd1]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xe0,0x17,0x84,0xd1]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x83,0x18,0xbf,0xd1]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xc5,0x3c,0x87,0xd1]
+
+[0x20,0x14,0xc2,0x9a]
+[0xe3,0x17,0xc4,0x9a]
+[0x1f,0x14,0xde,0x9a]
+[0x1e,0x14,0xdf,0x9a]
+
+# CHECK: gmi x0, x1, x2
+# CHECK: gmi x3, sp, x4
+# CHECK: gmi xzr, x0, x30
+# CHECK: gmi x30, x0, xzr
+
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x20,0x14,0xc2,0x9a]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xe3,0x17,0xc4,0x9a]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x1f,0x14,0xde,0x9a]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x1e,0x14,0xdf,0x9a]
+
+[0x20,0x00,0xc2,0x9a]
+[0x20,0x00,0xc2,0xba]
+[0xe0,0x03,0xdf,0x9a]
+[0xe0,0x03,0xdf,0xba]
+[0x1f,0x00,0xc1,0xba]
+[0xff,0x03,0xdf,0xba]
+
+# CHECK: subp x0, x1, x2
+# CHECK: subps x0, x1, x2
+# CHECK: subp x0, sp, sp
+# CHECK: subps x0, sp, sp
+# CHECK: subps xzr, x0, x1
+# CHECK: subps xzr, sp, sp
+
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x20,0x00,0xc2,0x9a]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x20,0x00,0xc2,0xba]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xe0,0x03,0xdf,0x9a]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xe0,0x03,0xdf,0xba]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x1f,0x00,0xc1,0xba]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xff,0x03,0xdf,0xba]
+
+[0x3f,0x08,0x30,0xd9]
+[0x5f,0xf8,0x2f,0xd9]
+[0xff,0x1b,0x20,0xd9]
+[0x3f,0x08,0x20,0xd9]
+
+# CHECK: stg [x1, #-4096]
+# CHECK: stg [x2, #4080]
+# CHECK: stg [sp, #16]
+# CHECK: stg [x1]
+
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x3f,0x08,0x30,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x5f,0xf8,0x2f,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xff,0x1b,0x20,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x3f,0x08,0x20,0xd9]
+
+[0x3f,0x08,0x70,0xd9]
+[0x5f,0xf8,0x6f,0xd9]
+[0xff,0x1b,0x60,0xd9]
+[0x3f,0x08,0x60,0xd9]
+
+# CHECK: stzg [x1, #-4096]
+# CHECK: stzg [x2, #4080]
+# CHECK: stzg [sp, #16]
+# CHECK: stzg [x1]
+
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x3f,0x08,0x70,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x5f,0xf8,0x6f,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xff,0x1b,0x60,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x3f,0x08,0x60,0xd9]
+
+[0x3f,0x0c,0x30,0xd9]
+[0x5f,0xfc,0x2f,0xd9]
+[0xff,0x1f,0x20,0xd9]
+
+# CHECK: stg [x1, #-4096]!
+# CHECK: stg [x2, #4080]!
+# CHECK: stg [sp, #16]!
+
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x3f,0x0c,0x30,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x5f,0xfc,0x2f,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xff,0x1f,0x20,0xd9]
+
+[0x3f,0x0c,0x70,0xd9]
+[0x5f,0xfc,0x6f,0xd9]
+[0xff,0x1f,0x60,0xd9]
+
+# CHECK: stzg [x1, #-4096]!
+# CHECK: stzg [x2, #4080]!
+# CHECK: stzg [sp, #16]!
+
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x3f,0x0c,0x70,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x5f,0xfc,0x6f,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xff,0x1f,0x60,0xd9]
+
+[0x3f,0x04,0x30,0xd9]
+[0x5f,0xf4,0x2f,0xd9]
+[0xff,0x17,0x20,0xd9]
+
+# CHECK: stg [x1], #-4096
+# CHECK: stg [x2], #4080
+# CHECK: stg [sp], #16
+
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x3f,0x04,0x30,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x5f,0xf4,0x2f,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xff,0x17,0x20,0xd9]
+
+[0x3f,0x04,0x70,0xd9]
+[0x5f,0xf4,0x6f,0xd9]
+[0xff,0x17,0x60,0xd9]
+
+# CHECK: stzg [x1], #-4096
+# CHECK: stzg [x2], #4080
+# CHECK: stzg [sp], #16
+
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x3f,0x04,0x70,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x5f,0xf4,0x6f,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xff,0x17,0x60,0xd9]
+
+[0x3f,0x08,0xb0,0xd9]
+[0x5f,0xf8,0xaf,0xd9]
+[0xff,0x1b,0xa0,0xd9]
+[0x3f,0x08,0xa0,0xd9]
+
+# CHECK: st2g [x1, #-4096]
+# CHECK: st2g [x2, #4080]
+# CHECK: st2g [sp, #16]
+# CHECK: st2g [x1]
+
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x3f,0x08,0xb0,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x5f,0xf8,0xaf,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xff,0x1b,0xa0,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x3f,0x08,0xa0,0xd9]
+
+[0x3f,0x08,0xf0,0xd9]
+[0x5f,0xf8,0xef,0xd9]
+[0xff,0x1b,0xe0,0xd9]
+[0x3f,0x08,0xe0,0xd9]
+
+# CHECK: stz2g [x1, #-4096]
+# CHECK: stz2g [x2, #4080]
+# CHECK: stz2g [sp, #16]
+# CHECK: stz2g [x1]
+
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x3f,0x08,0xf0,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x5f,0xf8,0xef,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xff,0x1b,0xe0,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x3f,0x08,0xe0,0xd9]
+
+[0x3f,0x0c,0xb0,0xd9]
+[0x5f,0xfc,0xaf,0xd9]
+[0xff,0x1f,0xa0,0xd9]
+
+# CHECK: st2g [x1, #-4096]!
+# CHECK: st2g [x2, #4080]!
+# CHECK: st2g [sp, #16]!
+
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x3f,0x0c,0xb0,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x5f,0xfc,0xaf,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xff,0x1f,0xa0,0xd9]
+
+[0x3f,0x0c,0xf0,0xd9]
+[0x5f,0xfc,0xef,0xd9]
+[0xff,0x1f,0xe0,0xd9]
+
+# CHECK: stz2g [x1, #-4096]!
+# CHECK: stz2g [x2, #4080]!
+# CHECK: stz2g [sp, #16]!
+
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x3f,0x0c,0xf0,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x5f,0xfc,0xef,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xff,0x1f,0xe0,0xd9]
+
+[0x3f,0x04,0xb0,0xd9]
+[0x5f,0xf4,0xaf,0xd9]
+[0xff,0x17,0xa0,0xd9]
+
+# CHECK: st2g [x1], #-4096
+# CHECK: st2g [x2], #4080
+# CHECK: st2g [sp], #16
+
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x3f,0x04,0xb0,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x5f,0xf4,0xaf,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xff,0x17,0xa0,0xd9]
+
+[0x3f,0x04,0xf0,0xd9]
+[0x5f,0xf4,0xef,0xd9]
+[0xff,0x17,0xe0,0xd9]
+
+# CHECK: stz2g [x1], #-4096
+# CHECK: stz2g [x2], #4080
+# CHECK: stz2g [sp], #16
+
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x3f,0x04,0xf0,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x5f,0xf4,0xef,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xff,0x17,0xe0,0xd9]
+
+[0x40,0x04,0x20,0x69]
+[0x40,0x84,0x1f,0x69]
+[0xe0,0x87,0x00,0x69]
+[0x5f,0x84,0x00,0x69]
+[0x40,0xfc,0x00,0x69]
+[0x40,0x7c,0x00,0x69]
+
+# CHECK: stgp x0, x1, [x2, #-1024]
+# CHECK: stgp x0, x1, [x2, #1008]
+# CHECK: stgp x0, x1, [sp, #16]
+# CHECK: stgp xzr, x1, [x2, #16]
+# CHECK: stgp x0, xzr, [x2, #16]
+# CHECK: stgp x0, xzr, [x2]
+
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x40,0x04,0x20,0x69]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x40,0x84,0x1f,0x69]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xe0,0x87,0x00,0x69]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x5f,0x84,0x00,0x69]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x40,0xfc,0x00,0x69]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x40,0x7c,0x00,0x69]
+
+[0x40,0x04,0xa0,0x69]
+[0x40,0x84,0x9f,0x69]
+[0xe0,0x87,0x80,0x69]
+[0x5f,0x84,0x80,0x69]
+[0x40,0xfc,0x80,0x69]
+
+# CHECK: stgp x0, x1, [x2, #-1024]!
+# CHECK: stgp x0, x1, [x2, #1008]!
+# CHECK: stgp x0, x1, [sp, #16]!
+# CHECK: stgp xzr, x1, [x2, #16]!
+# CHECK: stgp x0, xzr, [x2, #16]!
+
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x40,0x04,0xa0,0x69]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x40,0x84,0x9f,0x69]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xe0,0x87,0x80,0x69]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x5f,0x84,0x80,0x69]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x40,0xfc,0x80,0x69]
+
+[0x40,0x04,0xa0,0x68]
+[0x40,0x84,0x9f,0x68]
+[0xe0,0x87,0x80,0x68]
+[0x5f,0x84,0x80,0x68]
+[0x40,0xfc,0x80,0x68]
+
+# CHECK: stgp x0, x1, [x2], #-1024
+# CHECK: stgp x0, x1, [x2], #1008
+# CHECK: stgp x0, x1, [sp], #16
+# CHECK: stgp xzr, x1, [x2], #16
+# CHECK: stgp x0, xzr, [x2], #16
+
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x40,0x04,0xa0,0x68]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x40,0x84,0x9f,0x68]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xe0,0x87,0x80,0x68]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x5f,0x84,0x80,0x68]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x40,0xfc,0x80,0x68]
+
+[0x20,0x00,0x60,0xd9]
+[0xe2,0x03,0x70,0xd9]
+[0x83,0xf0,0x6f,0xd9]
+
+# CHECK: ldg x0, [x1]
+# CHECK: ldg x2, [sp, #-4096]
+# CHECK: ldg x3, [x4, #4080]
+
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x20,0x00,0x60,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xe2,0x03,0x70,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x83,0xf0,0x6f,0xd9]
+
+[0x20,0x00,0xe0,0xd9]
+[0xe1,0x03,0xe0,0xd9]
+[0x5f,0x00,0xe0,0xd9]
+[0x20,0x00,0xa0,0xd9]
+[0xe1,0x03,0xa0,0xd9]
+[0x5f,0x00,0xa0,0xd9]
+
+# CHECK: ldgv x0, [x1]!
+# CHECK: ldgv x1, [sp]!
+# CHECK: ldgv xzr, [x2]!
+# CHECK: stgv x0, [x1]!
+# CHECK: stgv x1, [sp]!
+# CHECK: stgv xzr, [x2]!
+
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x20,0x00,0xe0,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xe1,0x03,0xe0,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x5f,0x00,0xe0,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x20,0x00,0xa0,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0xe1,0x03,0xa0,0xd9]
+# NOMTE: warning: invalid instruction encoding
+# NOMTE-NEXT: [0x5f,0x00,0xa0,0xd9]
[0x60,0x76,0x08,0xd5]
[0x81,0x76,0x08,0xd5]
@@ -77,9 +503,19 @@
# CHECK: mrs x6, TFSR_EL12
# CHECK: mrs x7, TFSRE0_EL1
+# NOMTE: mrs x0, S3_3_C4_C2_7
+# NOMTE: mrs x1, S3_0_C1_C0_6
+# NOMTE: mrs x2, S3_0_C1_C0_5
+# NOMTE: mrs x3, S3_0_C6_C5_0
+# NOMTE: mrs x4, S3_4_C6_C5_0
+# NOMTE: mrs x5, S3_6_C6_C6_0
+# NOMTE: mrs x6, S3_5_C6_C6_0
+# NOMTE: mrs x7, S3_0_C6_C6_1
+
[0x9f,0x40,0x03,0xd5]
# CHECK: msr TCO, #0
+# NOMTE: msr S0_3_C4_C0_4, xzr
[0xe0,0x42,0x1b,0xd5]
[0xc1,0x10,0x18,0xd5]
@@ -98,3 +534,12 @@
# CHECK: msr TFSR_EL3, x5
# CHECK: msr TFSR_EL12, x6
# CHECK: msr TFSRE0_EL1, x7
+
+# NOMTE: msr S3_3_C4_C2_7, x0
+# NOMTE: msr S3_0_C1_C0_6, x1
+# NOMTE: msr S3_0_C1_C0_5, x2
+# NOMTE: msr S3_0_C6_C5_0, x3
+# NOMTE: msr S3_4_C6_C5_0, x4
+# NOMTE: msr S3_6_C6_C6_0, x5
+# NOMTE: msr S3_5_C6_C6_0, x6
+# NOMTE: msr S3_0_C6_C6_1, x7
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